x86_64: fix asm
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parent
0a3bcb57f6
commit
1383055b17
3 changed files with 19 additions and 14 deletions
31
x86_64-asm.c
31
x86_64-asm.c
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@ -117,14 +117,14 @@ typedef struct Operand {
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ExprValue e;
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ExprValue e;
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} Operand;
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} Operand;
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static const uint8_t reg_to_size[7] = {
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static const uint8_t reg_to_size[9] = {
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/*
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/*
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[OP_REG8] = 0,
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[OP_REG8] = 0,
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[OP_REG16] = 1,
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[OP_REG16] = 1,
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[OP_REG32] = 2,
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[OP_REG32] = 2,
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[OP_REG64] = 3,
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[OP_REG64] = 3,
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*/
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*/
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0, 0, 1, 0, 2, 0, 3
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0, 0, 1, 0, 2, 0, 0, 0, 3
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};
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};
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#define NB_TEST_OPCODES 30
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#define NB_TEST_OPCODES 30
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@ -493,23 +493,22 @@ static void asm_opcode(TCCState *s1, int opcode)
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if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
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if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
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continue;
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continue;
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} else if (pa->instr_type & OPC_ARITH) {
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} else if (pa->instr_type & OPC_ARITH) {
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if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 4))
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if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 5))
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continue;
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continue;
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goto compute_size;
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s = (opcode - pa->sym) % 5;
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} else if (pa->instr_type & OPC_SHIFT) {
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} else if (pa->instr_type & OPC_SHIFT) {
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if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 4))
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if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 5))
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continue;
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continue;
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goto compute_size;
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s = (opcode - pa->sym) % 5;
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} else if (pa->instr_type & OPC_TEST) {
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} else if (pa->instr_type & OPC_TEST) {
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if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
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if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
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continue;
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continue;
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} else if (pa->instr_type & OPC_B) {
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} else if (pa->instr_type & OPC_B) {
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if (!(opcode >= pa->sym && opcode <= pa->sym + 3))
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if (!(opcode >= pa->sym && opcode < pa->sym + 5))
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continue;
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continue;
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compute_size:
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s = opcode - pa->sym;
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s = (opcode - pa->sym) & 3;
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} else if (pa->instr_type & OPC_WLQ) {
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} else if (pa->instr_type & OPC_WLQ) {
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if (!(opcode >= pa->sym && opcode <= pa->sym + 2))
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if (!(opcode >= pa->sym && opcode < pa->sym + 4))
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continue;
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continue;
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s = opcode - pa->sym + 1;
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s = opcode - pa->sym + 1;
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} else {
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} else {
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@ -589,7 +588,11 @@ static void asm_opcode(TCCState *s1, int opcode)
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s = 1;
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s = 1;
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else if (s == 3) {
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else if (s == 3) {
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/* generate REX prefix */
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/* generate REX prefix */
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g(rex);
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if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
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(ops[0].type & OP_REG64))
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;
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else
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g(rex);
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s = 1;
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s = 1;
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}
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}
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/* now generates the operation */
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/* now generates the operation */
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@ -616,7 +619,7 @@ static void asm_opcode(TCCState *s1, int opcode)
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nb_ops = 0;
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nb_ops = 0;
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} else if (v <= 0x05) {
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} else if (v <= 0x05) {
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/* arith case */
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/* arith case */
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v += ((opcode - TOK_ASM_addb) >> 2) << 3;
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v += ((opcode - TOK_ASM_addb) / 5) << 3;
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} else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
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} else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
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/* fpu arith case */
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/* fpu arith case */
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v += ((opcode - pa->sym) / 6) << 3;
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v += ((opcode - pa->sym) / 6) << 3;
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@ -673,11 +676,11 @@ static void asm_opcode(TCCState *s1, int opcode)
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/* search which operand will used for modrm */
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/* search which operand will used for modrm */
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modrm_index = 0;
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modrm_index = 0;
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if (pa->instr_type & OPC_SHIFT) {
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if (pa->instr_type & OPC_SHIFT) {
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reg = (opcode - pa->sym) >> 2;
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reg = (opcode - pa->sym) / 5;
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if (reg == 6)
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if (reg == 6)
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reg = 7;
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reg = 7;
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} else if (pa->instr_type & OPC_ARITH) {
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} else if (pa->instr_type & OPC_ARITH) {
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reg = (opcode - pa->sym) >> 2;
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reg = (opcode - pa->sym) / 5;
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} else if (pa->instr_type & OPC_FARITH) {
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} else if (pa->instr_type & OPC_FARITH) {
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reg = (opcode - pa->sym) / 6;
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reg = (opcode - pa->sym) / 6;
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} else {
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} else {
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@ -109,6 +109,7 @@ ALT(DEF_ASM_OP2(movw, 0x0f26, 0, OPC_MODRM | OPC_WLQ, OPT_REG64, OPT_TR))
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ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REG32))
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ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REG32))
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ALT(DEF_ASM_OP2(movsbw, 0x0fbe, 0, OPC_MODRM | OPC_D16, OPT_REG8 | OPT_EA, OPT_REG16))
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ALT(DEF_ASM_OP2(movsbw, 0x0fbe, 0, OPC_MODRM | OPC_D16, OPT_REG8 | OPT_EA, OPT_REG16))
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ALT(DEF_ASM_OP2(movswl, 0x0fbf, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
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ALT(DEF_ASM_OP2(movswl, 0x0fbf, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
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ALT(DEF_ASM_OP2(movslq, 0x4863, 0, OPC_MODRM, OPT_REG32 | OPT_EA, OPT_REG))
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ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM | OPC_WL, OPT_REG8 | OPT_EA, OPT_REGW))
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ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM | OPC_WL, OPT_REG8 | OPT_EA, OPT_REGW))
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ALT(DEF_ASM_OP2(movzwl, 0x0fb7, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
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ALT(DEF_ASM_OP2(movzwl, 0x0fb7, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
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@ -146,6 +146,7 @@
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DEF_ASM(movsbw)
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DEF_ASM(movsbw)
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DEF_ASM(movsbl)
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DEF_ASM(movsbl)
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DEF_ASM(movswl)
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DEF_ASM(movswl)
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DEF_ASM(movslq)
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DEF_WLQ(lea)
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DEF_WLQ(lea)
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