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arm-asm: Raise error if asm_data_processing_opcode and asm_shift_opcode try to use PC for register-controlled shifts

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Danny Milosavljevic 2020-12-27 21:17:01 +01:00
parent 79567004b4
commit 86cc9c587b
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GPG key ID: E71A35542C30BAA5
1 changed files with 17 additions and 2 deletions
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19
arm-asm.c
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@ -529,6 +529,13 @@ static void asm_data_processing_opcode(TCCState *s1, int token)
return; return;
} else { } else {
uint32_t opcode = 0; uint32_t opcode = 0;
if (nb_shift && shift.type == OP_REG32) {
if ((ops[0].type == OP_REG32 && ops[0].reg == 15) ||
(ops[1].type == OP_REG32 && ops[1].reg == 15)) {
tcc_error("Using the 'pc' register in data processing instructions that have a register-controlled shift is not implemented by ARM");
return;
}
}
// data processing (general case): // data processing (general case):
// operands: // operands:
@ -655,9 +662,10 @@ static void asm_shift_opcode(TCCState *s1, int token)
return; return;
} }
if (ops[0].type != OP_REG32) if (ops[0].type != OP_REG32) {
expect("(destination operand) register"); expect("(destination operand) register");
else return;
} else
operands |= ENCODE_RD(ops[0].reg); operands |= ENCODE_RD(ops[0].reg);
if (nb_ops == 2) { if (nb_ops == 2) {
@ -694,6 +702,13 @@ static void asm_shift_opcode(TCCState *s1, int token)
break; break;
} }
if (ops[2].type == OP_REG32) {
if ((ops[0].type == OP_REG32 && ops[0].reg == 15) ||
(ops[1].type == OP_REG32 && ops[1].reg == 15)) {
tcc_error("Using the 'pc' register in data processing instructions that have a register-controlled shift is not implemented by ARM");
}
}
if (operands & ENCODE_IMMEDIATE_FLAG) if (operands & ENCODE_IMMEDIATE_FLAG)
operands |= asm_encode_rotation(&ops[2]); operands |= asm_encode_rotation(&ops[2]);
else else