x86-asm: Reorganize instr_type
Disjoint instruction types don't need to be a bit field, so introduce an enumeration (3 bits). Also the 0x0f prefix can be expressed by a bit, doesn't need a byte in the opcode field. That enables to encode further prefixes still in 16 bit. To not have to touch all insns do some macro fiddling filtering out a 0x0f byte in the second position.
This commit is contained in:
Michael Matz
parent
4af6e087dd
commit
bde802df29
3 changed files with 65 additions and 46 deletions
107
i386-asm.c
107
i386-asm.c
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@ -29,19 +29,26 @@
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#define TOK_ASM_last TOK_ASM_emms
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#define TOK_ASM_alllast TOK_ASM_subps
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#define OPC_JMP 0x01 /* jmp operand */
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#define OPC_B 0x02 /* only used with OPC_WL */
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#define OPC_WL 0x04 /* accepts w, l or no suffix */
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#define OPC_B 0x01 /* only used with OPC_WL */
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#define OPC_WL 0x02 /* accepts w, l or no suffix */
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#define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
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#define OPC_REG 0x08 /* register is added to opcode */
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#define OPC_MODRM 0x10 /* modrm encoding */
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#define OPC_FWAIT 0x20 /* add fwait opcode */
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#define OPC_TEST 0x40 /* test opcodes */
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#define OPC_SHIFT 0x80 /* shift opcodes */
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#define OPC_D16 0x0100 /* generate data16 prefix */
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#define OPC_ARITH 0x0200 /* arithmetic opcodes */
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#define OPC_SHORTJMP 0x0400 /* short jmp operand */
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#define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
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#define OPC_REG 0x04 /* register is added to opcode */
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#define OPC_MODRM 0x08 /* modrm encoding */
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#define OPCT_MASK 0x70
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#define OPC_FWAIT 0x10 /* add fwait opcode */
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#define OPC_SHIFT 0x20 /* shift opcodes */
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#define OPC_ARITH 0x30 /* arithmetic opcodes */
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#define OPC_FARITH 0x40 /* FPU arithmetic opcodes */
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#define OPC_TEST 0x50 /* test opcodes */
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#define OPC_JMP_TEST 0x60 /* A test and jmp opcode */
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#define OPC_JMP 0x70 /* A non-testing jmp opcode */
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#define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
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#define OPC_SHORTJMP 0x80 /* short jmp operand */
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#define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
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#define OPC_D16 0x0800 /* generate data16 prefix */
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#ifdef TCC_TARGET_X86_64
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# define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
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# define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
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@ -211,11 +218,15 @@ static const uint8_t segment_prefixes[] = {
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static const ASMInstr asm_instrs[] = {
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#define ALT(x) x
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/* This removes a 0x0f in the second byte */
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#define O(o) ((((o) & 0xff00) == 0x0f00) ? ((((o) >> 8) & ~0xff) | ((o) & 0xff)) : (o))
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/* This constructs instr_type from opcode, type and group. */
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#define T(o,i,g) ((i) | ((g) << OPC_GROUP_SHIFT) | ((((o) & 0xff00) == 0x0f00) ? OPC_0F : 0))
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#define DEF_ASM_OP0(name, opcode)
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#define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
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#define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
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#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
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#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
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#define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 0 },
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#define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 1, { op0 }},
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#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 2, { op0, op1 }},
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#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 3, { op0, op1, op2 }},
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#ifdef TCC_TARGET_X86_64
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# include "x86_64-asm.h"
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#else
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@ -594,12 +605,13 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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/* optimize matching by using a lookup table (no hashing is needed
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!) */
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for(pa = asm_instrs; pa->sym != 0; pa++) {
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int it = pa->instr_type & OPCT_MASK;
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s = 0;
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if (pa->instr_type & OPC_FARITH) {
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if (it == OPC_FARITH) {
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v = opcode - pa->sym;
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if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
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continue;
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} else if (pa->instr_type & OPC_ARITH) {
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} else if (it == OPC_ARITH) {
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if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
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continue;
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s = (opcode - pa->sym) % NBWLX;
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@ -612,11 +624,11 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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continue;
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s++;
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}
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} else if (pa->instr_type & OPC_SHIFT) {
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} else if (it == OPC_SHIFT) {
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if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
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continue;
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s = (opcode - pa->sym) % NBWLX;
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} else if (pa->instr_type & OPC_TEST) {
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} else if (it == OPC_TEST || it == OPC_JMP_TEST) {
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if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
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continue;
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/* cmovxx is a test opcode but accepts multiple sizes.
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@ -650,7 +662,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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should only be done if we really have an >32bit imm64, and that
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is hardcoded. Ignore it here. */
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if (pa->opcode == 0xb0 && ops[0].type != OP_IM64
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&& ops[1].type == OP_REG64)
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&& ops[1].type == OP_REG64
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&& !(pa->instr_type & OPC_0F))
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continue;
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#endif
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/* now decode and check each operand */
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@ -777,12 +790,14 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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#endif
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/* now generates the operation */
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if (pa->instr_type & OPC_FWAIT)
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if (OPCT_IS(pa->instr_type, OPC_FWAIT))
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g(0x9b);
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if (seg_prefix)
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g(seg_prefix);
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v = pa->opcode;
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if (pa->instr_type & OPC_0F)
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v = ((v & ~0xff) << 8) | 0x0f00 | (v & 0xff);
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if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
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/* kludge for imul $im, %reg */
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nb_ops = 3;
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@ -802,25 +817,23 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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} else if (v <= 0x05) {
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/* arith case */
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v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
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} else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
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} else if ((pa->instr_type & (OPCT_MASK | OPC_MODRM)) == OPC_FARITH) {
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/* fpu arith case */
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v += ((opcode - pa->sym) / 6) << 3;
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}
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if (pa->instr_type & OPC_REG) {
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/* mov $im, %reg case */
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if (v == 0xb0 && s >= 1)
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v += 7;
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for(i = 0; i < nb_ops; i++) {
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if (op_type[i] & (OP_REG | OP_ST)) {
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v += ops[i].reg;
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break;
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}
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}
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/* mov $im, %reg case */
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if (pa->opcode == 0xb0 && s >= 1)
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v += 7;
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}
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if (pa->instr_type & OPC_B)
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v += s >= 1;
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if (pa->instr_type & OPC_TEST)
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v += test_bits[opcode - pa->sym];
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if (pa->instr_type & OPC_SHORTJMP) {
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Sym *sym;
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int jmp_disp;
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@ -839,32 +852,36 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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op_type[0] = OP_IM8S;
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} else {
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no_short_jump:
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if (pa->instr_type & OPC_JMP) {
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/* long jump will be allowed. need to modify the
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opcode slightly */
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if (v == 0xeb)
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v = 0xe9;
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else
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v += 0x0f10;
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} else {
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tcc_error("invalid displacement");
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}
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/* long jump will be allowed. need to modify the
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opcode slightly */
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if (v == 0xeb) /* jmp */
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v = 0xe9;
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else if (v == 0x70) /* jcc */
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v += 0x0f10;
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else
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tcc_error("invalid displacement");
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}
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}
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op1 = v >> 8;
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if (OPCT_IS(pa->instr_type, OPC_TEST)
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|| OPCT_IS(pa->instr_type, OPC_JMP_TEST))
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v += test_bits[opcode - pa->sym];
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op1 = v >> 16;
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if (op1)
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g(op1);
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op1 = (v >> 8) & 0xff;
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if (op1)
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g(op1);
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g(v);
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/* search which operand will used for modrm */
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modrm_index = 0;
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if (pa->instr_type & OPC_SHIFT) {
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if (OPCT_IS(pa->instr_type, OPC_SHIFT)) {
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reg = (opcode - pa->sym) / NBWLX;
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if (reg == 6)
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reg = 7;
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} else if (pa->instr_type & OPC_ARITH) {
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} else if (OPCT_IS(pa->instr_type, OPC_ARITH)) {
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reg = (opcode - pa->sym) / NBWLX;
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} else if (pa->instr_type & OPC_FARITH) {
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} else if (OPCT_IS(pa->instr_type, OPC_FARITH)) {
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reg = (opcode - pa->sym) / 6;
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} else {
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reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
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@ -902,7 +919,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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/* emit constants */
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#ifndef TCC_TARGET_X86_64
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if (pa->opcode == 0x9a || pa->opcode == 0xea) {
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if (!(pa->instr_type & OPC_0F)
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&& (pa->opcode == 0x9a || pa->opcode == 0xea)) {
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/* ljmp or lcall kludge */
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gen_expr32(&ops[1].e);
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if (ops[0].e.sym)
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@ -938,7 +956,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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} else if (v & OP_IM64) {
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gen_expr64(&ops[i].e);
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#endif
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} else if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
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} else if (OPCT_IS (pa->instr_type, OPC_JMP)
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|| OPCT_IS (pa->instr_type, OPC_JMP_TEST)) {
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gen_disp32(&ops[i].e);
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} else {
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gen_expr32(&ops[i].e);
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@ -221,7 +221,7 @@ ALT(DEF_ASM_OP1(ret, 0xc2, 0, 0, OPT_IM16))
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DEF_ASM_OP0(lret, 0xcb)
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ALT(DEF_ASM_OP1(lret, 0xca, 0, 0, OPT_IM16))
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ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP | OPC_JMP | OPC_TEST, OPT_ADDR))
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ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP | OPC_JMP_TEST, OPT_ADDR))
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DEF_ASM_OP1(loopne, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loopnz, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loope, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
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@ -226,7 +226,7 @@ ALT(DEF_ASM_OP1(retq, 0xc2, 0, 0, OPT_IM16))
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DEF_ASM_OP0(lret, 0xcb)
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ALT(DEF_ASM_OP1(lret, 0xca, 0, 0, OPT_IM16))
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ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP | OPC_JMP | OPC_TEST, OPT_ADDR))
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ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP | OPC_JMP_TEST, OPT_ADDR))
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DEF_ASM_OP1(loopne, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loopnz, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loope, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
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