arm-asm: Add vldr, vstr
Also add s0...s31, d0...d15
This commit is contained in:
Danny Milosavljevic
parent
31dde11ad5
commit
cdbb55396c
3 changed files with 169 additions and 1 deletions
97
arm-asm.c
97
arm-asm.c
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@ -1444,6 +1444,97 @@ static void asm_coprocessor_data_transfer_opcode(TCCState *s1, int token)
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}
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}
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#if defined(TCC_ARM_VFP)
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#define CP_SINGLE_PRECISION_FLOAT 10
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#define CP_DOUBLE_PRECISION_FLOAT 11
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/* Read the VFP register referred to by T.
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If OK, returns its number.
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If not OK, returns -1. */
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static int asm_parse_vfp_regvar(int t, int double_precision)
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{
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if (double_precision) {
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if (t >= TOK_ASM_d0 && t <= TOK_ASM_d15)
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return t - TOK_ASM_d0;
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} else {
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if (t >= TOK_ASM_s0 && t <= TOK_ASM_s31)
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return t - TOK_ASM_s0;
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}
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return -1;
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}
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static void asm_floating_point_single_data_transfer_opcode(TCCState *s1, int token)
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{
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Operand ops[3];
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uint8_t coprocessor = 0;
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uint8_t coprocessor_destination_register = 0;
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int long_transfer = 0;
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int reg;
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// Note: vldr p1, c0, [r4, #4] ; simple offset: r0 = *(int*)(r4+4); r4 unchanged
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// Note: Not allowed: vldr p2, c0, [r4, #4]! ; pre-indexed: r0 = *(int*)(r4+4); r4 = r4+4
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// Note: Not allowed: vldr p3, c0, [r4], #4 ; post-indexed: r0 = *(int*)(r4+0); r4 = r4+4
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if ((reg = asm_parse_vfp_regvar(tok, 0)) != -1) {
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coprocessor = CP_SINGLE_PRECISION_FLOAT;
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coprocessor_destination_register = reg;
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long_transfer = coprocessor_destination_register & 1;
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coprocessor_destination_register >>= 1;
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next();
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} else if ((reg = asm_parse_vfp_regvar(tok, 1)) != -1) {
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coprocessor = CP_DOUBLE_PRECISION_FLOAT;
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coprocessor_destination_register = reg;
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next();
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} else {
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expect("floating point register");
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return;
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}
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if (tok == ',')
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next();
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else
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expect("','");
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if (tok != '[')
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expect("'['");
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else
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next(); // skip '['
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parse_operand(s1, &ops[1]);
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if (ops[1].type != OP_REG32) {
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expect("(first source operand) register");
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return;
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}
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if (tok == ',') {
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next(); // skip ','
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parse_operand(s1, &ops[2]);
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if (ops[2].type != OP_IM8 && ops[2].type != OP_IM8N) {
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expect("immediate offset");
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return;
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}
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} else {
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// end of input expression in brackets--assume 0 offset
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ops[2].type = OP_IM8;
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ops[2].e.v = 0;
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}
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if (tok != ']')
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expect("']'");
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else
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next(); // skip ']'
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switch (ARM_INSTRUCTION_GROUP(token)) {
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case TOK_ASM_vldreq:
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asm_emit_coprocessor_data_transfer(condition_code_of_token(token), coprocessor, coprocessor_destination_register, &ops[1], &ops[2], 0, 1, 0, long_transfer, 1);
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break;
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case TOK_ASM_vstreq:
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asm_emit_coprocessor_data_transfer(condition_code_of_token(token), coprocessor, coprocessor_destination_register, &ops[1], &ops[2], 0, 1, 0, long_transfer, 0);
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break;
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default:
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expect("floating point data transfer instruction");
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}
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}
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#endif
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static void asm_misc_single_data_transfer_opcode(TCCState *s1, int token)
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{
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Operand ops[3];
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@ -1785,6 +1876,12 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
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case TOK_ASM_stcleq:
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return asm_coprocessor_data_transfer_opcode(s1, token);
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#if defined(TCC_ARM_VFP)
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case TOK_ASM_vldreq:
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case TOK_ASM_vstreq:
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return asm_floating_point_single_data_transfer_opcode(s1, token);
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#endif
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default:
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expect("known instruction");
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}
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59
arm-tok.h
59
arm-tok.h
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@ -66,6 +66,60 @@
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DEF_ASM(c14)
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DEF_ASM(c15)
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/* single-precision VFP registers */
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DEF_ASM(s0)
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DEF_ASM(s1)
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DEF_ASM(s2)
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DEF_ASM(s3)
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DEF_ASM(s4)
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DEF_ASM(s5)
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DEF_ASM(s6)
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DEF_ASM(s7)
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DEF_ASM(s8)
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DEF_ASM(s9)
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DEF_ASM(s10)
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DEF_ASM(s11)
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DEF_ASM(s12)
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DEF_ASM(s13)
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DEF_ASM(s14)
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DEF_ASM(s15)
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DEF_ASM(s16)
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DEF_ASM(s17)
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DEF_ASM(s18)
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DEF_ASM(s19)
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DEF_ASM(s20)
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DEF_ASM(s21)
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DEF_ASM(s22)
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DEF_ASM(s23)
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DEF_ASM(s24)
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DEF_ASM(s25)
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DEF_ASM(s26)
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DEF_ASM(s27)
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DEF_ASM(s28)
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DEF_ASM(s29)
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DEF_ASM(s30)
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DEF_ASM(s31)
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/* double-precision VFP registers */
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DEF_ASM(d0)
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DEF_ASM(d1)
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DEF_ASM(d2)
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DEF_ASM(d3)
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DEF_ASM(d4)
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DEF_ASM(d5)
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DEF_ASM(d6)
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DEF_ASM(d7)
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DEF_ASM(d8)
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DEF_ASM(d9)
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DEF_ASM(d10)
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DEF_ASM(d11)
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DEF_ASM(d12)
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DEF_ASM(d13)
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DEF_ASM(d14)
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DEF_ASM(d15)
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/* data processing directives */
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DEF_ASM(asl)
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@ -225,3 +279,8 @@
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DEF_ASM_CONDED(cdp)
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DEF_ASM_CONDED(mcr)
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DEF_ASM_CONDED(mrc)
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// Floating point high-level instructions
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DEF_ASM_CONDED(vldr)
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DEF_ASM_CONDED(vstr)
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@ -5,8 +5,14 @@ set -e
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# Note: "{r3}" is definitely different--but would complicate the assembler.
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state="`mktemp -d`"
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cat ../arm-tok.h |grep DEF_ASM |grep -v 'not useful' |grep -v '#define' |grep -v '/[*]' |sed -e 's;^[ ]*DEF_ASM[^(]*(\(.*\)).*$;\1;' | egrep -v '^((r|c|p)[0-9]+|fp|ip|sp|lr|pc|asl)$' | while read s
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cat ../arm-tok.h |grep DEF_ASM |grep -v 'not useful' |grep -v '#define' |grep -v '/[*]' |sed -e 's;^[ ]*DEF_ASM[^(]*(\(.*\)).*$;\1;' | egrep -v '^((r|c|p|s|d)[0-9]+|fp|ip|sp|lr|pc|asl)$' | while read s
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do
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# If VFP is disabled, skip VFP tests.
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if [ "${s#v}" != "${s}" ] && ! grep -q "CONFIG_arm_vfp=yes" ../config.mak
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then
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echo "note: skipping VFP instruction: $s (because VFP is disabled)">&2
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continue
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fi
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ok=0
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for args in "r3, r4, r5, r6" \
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"r3, r4, r5" \
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@ -103,6 +109,12 @@ do
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"p5, c2, [r3, #-4]" \
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"p5, c2, [r3, #0x45]" \
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"p5, c2, [r3, #-0x45]" \
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"s2, [r3]" \
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"s3, [r4]" \
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"s2, [r3, #4]" \
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"s2, [r3, #-4]" \
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"s2, [r3, #0x45]" \
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"s2, [r3, #-0x45]" \
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""
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do
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#echo ".syntax unified" > a.s
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