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x86-asm: Implement fxrstorq and fxsaveq

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This commit is contained in:
Michael Matz 2016-07-11 18:53:44 +02:00
parent 2b618c1ab4
commit f6c1eb10e2
2 changed files with 8 additions and 0 deletions
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2
tests/asmtest.S
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@ -614,6 +614,8 @@ int $0x10
mfence mfence
sfence sfence
clflush 0x1000(%rax,%rcx) clflush 0x1000(%rax,%rcx)
fxsaveq (%rdx)
fxrstorq (%rcx)
#endif #endif
emms emms

6
x86_64-asm.h
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@ -347,6 +347,12 @@ ALT(DEF_ASM_OP1(fstsw, 0xdd, 7, OPC_MODRM | OPC_FWAIT, OPT_EA ))
DEF_ASM_OP1(ffreep, 0xdfc0, 4, OPC_REG, OPT_ST ) DEF_ASM_OP1(ffreep, 0xdfc0, 4, OPC_REG, OPT_ST )
DEF_ASM_OP1(fxsave, 0x0fae, 0, OPC_MODRM, OPT_EA ) DEF_ASM_OP1(fxsave, 0x0fae, 0, OPC_MODRM, OPT_EA )
DEF_ASM_OP1(fxrstor, 0x0fae, 1, OPC_MODRM, OPT_EA ) DEF_ASM_OP1(fxrstor, 0x0fae, 1, OPC_MODRM, OPT_EA )
/* The *q forms of fxrstor/fxsave use a REX prefix.
If the operand would use extended registers we would have to modify
it instead of generating a second one. Currently that's no
problem with TCC, we don't use extended registers. */
DEF_ASM_OP1(fxsaveq, 0x480fae, 0, OPC_MODRM, OPT_EA )
DEF_ASM_OP1(fxrstorq, 0x480fae, 1, OPC_MODRM, OPT_EA )
/* segments */ /* segments */
DEF_ASM_OP2(arpl, 0x63, 0, OPC_MODRM, OPT_REG16, OPT_REG16 | OPT_EA) DEF_ASM_OP2(arpl, 0x63, 0, OPC_MODRM, OPT_REG16, OPT_REG16 | OPT_EA)