Rework instruction encoding
This commit is contained in:
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3b0e785644
commit
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doc/isa.org
86
doc/isa.org
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@ -5,7 +5,6 @@
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- PC :: Program counter (32bit)
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- PC :: Program counter (32bit)
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- A :: Accumulator (32bit)
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- A :: Accumulator (32bit)
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- D :: Direct register (32bit)
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- X :: X index register (32bit)
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- X :: X index register (32bit)
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- Y :: Y index register (32bit)
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- Y :: Y index register (32bit)
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- SR :: status register (8bit)
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- SR :: status register (8bit)
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@ -14,10 +13,10 @@
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Status register flags
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Status register flags
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#+begin_src
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#+begin_src
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31 0
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7 0
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+------ .... ----+-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+
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| |N|V| |B|D|I|Z|C|
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|N|V|0|B|D|0|Z|C|
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+------ .... ----+-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+
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#+end_src
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#+end_src
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- N :: Negative
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- N :: Negative
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@ -26,11 +25,12 @@ Status register flags
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The overflow flag (V) indicates overflow with signed binary arithmetics.
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The overflow flag (V) indicates overflow with signed binary arithmetics.
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- B :: Break
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- B :: Break
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- D :: Decimal
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- D :: Decimal
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- I :: Interrupt
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- Z :: Zero
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- Z :: Zero
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The zero flag (Z) indicates a value of all zero bits.
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The zero flag (Z) indicates a value of all zero bits.
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- C :: Carry
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- C :: Carry
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** Control Registers
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** Addressing Modes
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** Addressing Modes
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*** Implied Addressing
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*** Implied Addressing
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@ -53,38 +53,50 @@ A size and a literal operand is given immediately after the instruction.
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** Opcodes
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** Opcodes
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| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
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| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
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|----|----------|-----------|-------|----|----|----|----|----|----------|-----------|----------|----|-----------|-----------|-----------|----|
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|----|----------|-----------|-------|--------|----|----|----|----|----------|-----------|----------|----|-----------|-----------|-----------|----|
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| 0- | BRK impl | ORA X,ind | | | | | | | PHP impl | ORA # | ASL A | | | ORA abs | ASL abs | |
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| 0- | BRK impl | ORA X,ind | | prefix | | | | prefix | PHP impl | ORA # | ASL A | | | ORA abs | ASL abs | |
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| 1- | BPL rel | ORA ind,Y | | | | | | | CLC impl | ORA abs,Y | | | | ORA abs,X | ASL abs,X | |
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| 1- | BPL rel | ORA ind,Y | | prefix | | | | prefix | CLC impl | ORA abs,Y | | | | ORA abs,X | ASL abs,X | |
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| 2- | JSR abs | AND X,ind | | | | | | | PLP impl | AND # | ROL A | | BIT abs | AND abs | ROL abs | |
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| 2- | JSR abs | AND X,ind | | prefix | | | | prefix | PLP impl | AND # | ROL A | | BIT abs | AND abs | ROL abs | |
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| 3- | BMI rel | AND ind,Y | | | | | | | SEC impl | AND abs,Y | | | | AND abs,X | ROL abs,X | |
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| 3- | BMI rel | AND ind,Y | | prefix | | | | prefix | SEC impl | AND abs,Y | | | | AND abs,X | ROL abs,X | |
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| 4- | RTI impl | EOR X,ind | | | | | | | PHA impl | EOR # | LSR A | | JMP abs | EOR abs | LSR abs | |
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| 4- | RTI impl | EOR X,ind | | prefix | | | | prefix | PHA impl | EOR # | LSR A | | JMP abs | EOR abs | LSR abs | |
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| 5- | BVC rel | EOR ind,Y | | | | | | | CLI impl | EOR abs,Y | | | | EOR abs,X | LSR abs,X | |
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| 5- | BVC rel | EOR ind,Y | | prefix | | | | prefix | CLI impl | EOR abs,Y | | | | EOR abs,X | LSR abs,X | |
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| 6- | RTS impl | ADC X,ind | PER? | | | | | | PLA impl | ADC # | ROR A | | JMP ind | ADC abs | ROR abs | |
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| 6- | RTS impl | ADC X,ind | PER? | prefix | | | | prefix | PLA impl | ADC # | ROR A | | JMP ind | ADC abs | ROR abs | |
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| 7- | BVS rel | ADC ind,Y | | | | | | | SEI impl | ADC abs,Y | | | | ADC abs,X | ROR abs,X | |
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| 7- | BVS rel | ADC ind,Y | | prefix | | | | prefix | SEI impl | ADC abs,Y | | | | ADC abs,X | ROR abs,X | |
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| 8- | | STA X,ind | | | | | | | DEY impl | | TXA impl | | STY abs | STA abs | STX abs | |
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| 8- | | STA X,ind | | prefix | | | | prefix | DEY impl | | TXA impl | | STY abs | STA abs | STX abs | |
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| 9- | BCC rel | STA ind,Y | | | | | | | TYA impl | STA abs,Y | TXS impl | | | STA abs,X | | |
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| 9- | BCC rel | STA ind,Y | | prefix | | | | prefix | TYA impl | STA abs,Y | TXS impl | | | STA abs,X | | |
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| A- | LDY # | LDA X,ind | LDX # | | | | | | TAY impl | LDA # | TAX impl | | LDY abs | LDA abs | LDX abs | |
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| A- | LDY # | LDA X,ind | LDX # | prefix | | | | prefix | TAY impl | LDA # | TAX impl | | LDY abs | LDA abs | LDX abs | |
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| B- | BCS rel | LDA ind,Y | | | | | | | CLV impl | LDA abs,Y | TSX impl | | LDY abs,X | LDA abs,X | LDX abs,Y | |
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| B- | BCS rel | LDA ind,Y | | prefix | | | | prefix | CLV impl | LDA abs,Y | TSX impl | | LDY abs,X | LDA abs,X | LDX abs,Y | |
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| C- | CPY # | CMP X,ind | | | | | | | INY impl | CMP # | DEX impl | | CPY abs | CMP abs | DEC abs | |
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| C- | CPY # | CMP X,ind | | prefix | | | | prefix | INY impl | CMP # | DEX impl | | CPY abs | CMP abs | DEC abs | |
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| D- | BNE rel | CMP ind,Y | | | | | | | CLD impl | CMP abs,Y | | | | CMP abs,X | DEC abs,X | |
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| D- | BNE rel | CMP ind,Y | | prefix | | | | prefix | CLD impl | CMP abs,Y | | | | CMP abs,X | DEC abs,X | |
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| E- | CPX # | SBC X,ind | | | | | | | INX impl | SBC # | NOP impl | | CPX abs | SBC abs | INC abs | |
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| E- | CPX # | SBC X,ind | | prefix | | | | prefix | INX impl | SBC # | NOP impl | | CPX abs | SBC abs | INC abs | |
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| F- | BEQ rel | SBC ind,Y | | | | | | | SED impl | SBC abs,Y | | | | SBC abs,X | INC abs,X | |
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| F- | BEQ rel | SBC ind,Y | | prefix | | | | prefix | SED impl | SBC abs,Y | | | | SBC abs,X | INC abs,X | |
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** Instruction encoding
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** Instruction encoding
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| 0-7 |
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*** Prefix
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|--------|
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| opcode |
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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|---|---|---|---|---|---|---|---|
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| A | A | OS | OS | 0 | S | 1 | 1 |
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- OS :: Size
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- 00 8bit
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- 01 16bit
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- 10 32bit
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- 11 64bit
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- A :: Address Size
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- S :: sign-extension
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#+begin_src
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8bits 8bits 8/16/32/64bits
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+--------+--------+-------...---+
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| prefix | opcode | value |
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+--------+--------+-------...---+
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#+end_src
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| 0-7 | 8-21 |
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|--------|---------------|
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| opcode | relative addr |
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| 0-7 | 8-15 | 16-X |
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|--------|------|-------|
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| opcode | attr | value |
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** Instructions Listing
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** Instructions Listing
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@ -93,4 +105,10 @@ A size and a literal operand is given immediately after the instruction.
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- ASL :: arithmetic shift left
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- ASL :: arithmetic shift left
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- BCC :: branch on carry clear
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- BCC :: branch on carry clear
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- BCS :: branch on carry set
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- BCS :: branch on carry set
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- BEQ :: branch on equa (zero set)
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- BEQ :: branch on equal (zero set)
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- BIT :: bitwise test with accumulator
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- BMI :: branch on minus
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- BNE :: branch not equal
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- BPL :: Branch on plus
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- BRK ::
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- BSR ::
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@ -1,3 +1,3 @@
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noinst_LIBRARIES = lib65oo2.a
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noinst_LIBRARIES = lib65oo2.a
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lib65oo2_a_SOURCES = op.c
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lib65oo2_a_SOURCES = op.c mnemonic.c
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19
lib/addressing.h
Normal file
19
lib/addressing.h
Normal file
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@ -0,0 +1,19 @@
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#ifndef LIB_65oo2_ADDRESSING_H
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# define LIB_65oo2_ADDRESSING_H 1
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typedef enum
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{
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ADDRESSING_NONE,
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ADDRESSING_IMPLIED,
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ADDRESSING_ACCUMULATOR,
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ADDRESSING_ABSOLUTE_X,
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ADDRESSING_ABSOLUTE_Y,
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ADDRESSING_IMMEDIATE,
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ADDRESSING_INDIRECT,
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ADDRESSING_X_INDIRECT,
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ADDRESSING_INDIRECT_Y,
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ADDRESSING_RELATIVE,
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ADDRESSING_MAX
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} AddressingMode;
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#endif /* !LIB_65oo2_ADDRESSING_H */
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0
lib/decoder.c
Normal file
0
lib/decoder.c
Normal file
33
lib/decoder.h
Normal file
33
lib/decoder.h
Normal file
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@ -0,0 +1,33 @@
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#ifndef LIB_65oo2_DECODER_H
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# define LIB_65oo2_DECODER_H 1
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#include <stddef.h>
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#include <stdint.h>
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#include "mnemonic.h"
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#include "addressing.h"
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typedef enum {
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ADDRESS_SIZE_HINT_NONE, /* default 8bits */
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ADDRESS_SIZE_HINT_16,
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ADDRESS_SIZE_HINT_32,
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ADDRESS_SIZE_HINT_MAX
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} AddressSizeHint;
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typedef enum {
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OPERAND_SIZE_HINT_NONE,
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OPERAND_SIZE_HINT_16,
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OPERAND_SIZE_HINT_32,
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OPERAND_SIZE_HINT_MAX
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} OperandSizeHint;
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typedef struct {
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Mnemonic mnemonic;
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uint8_t length;
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AddressingMode addressing;
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} DecodedInstruction;
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int decoder_decode(uint8_t *buffer, size_t length, DecodedInstruction *instruction);
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#endif /* !LIB_65oo2_DECODER_H */
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0
lib/disassembler.h
Normal file
0
lib/disassembler.h
Normal file
72
lib/mnemonic.c
Normal file
72
lib/mnemonic.c
Normal file
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@ -0,0 +1,72 @@
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#include "mnemonic.h"
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static const char *MNEMONIC_STR[MNEMONIC_MAX] = {
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"invalid",
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"adc",
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"and",
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"asl",
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"bcc",
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"bcs",
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"beq",
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"bit",
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"bmi",
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"bne",
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"bpl",
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"brk",
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"bvc",
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"bvs",
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"clc",
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"cld",
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"cli",
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"clv",
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"cmp",
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"cpx",
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"cpy",
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"dec",
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"dex",
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"dey",
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"eor",
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"inc",
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"inx",
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"iny",
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"jmp",
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"jsr",
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"lda",
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"ldx",
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"ldy",
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"lsr",
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"nop",
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"ora",
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"pha",
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"php",
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"pla",
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"plp",
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"rol",
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"ror",
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"rti",
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"rts",
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"sbc",
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"sec",
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"sed",
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"sei",
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"sta",
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"stx",
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"sty",
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"tax",
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"tay",
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"tsx",
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"txa",
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"txs",
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"tya"
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};
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const char *
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mnemonic_to_string(Mnemonic mnemonic)
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{
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if (mnemonic >= MNEMONIC_MAX)
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{
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return (MNEMONIC_STR[MNEMONIC_INVALID]);
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}
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return (MNEMONIC_STR[mnemonic]);
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}
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84
lib/mnemonic.h
Normal file
84
lib/mnemonic.h
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@ -0,0 +1,84 @@
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#ifndef LIB_65oo2_MNEMONIC_H
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# define LIB_65oo2_MNEMONIC_H 1
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typedef enum {
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MNEMONIC_INVALID,
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/** add with carry */
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MNEMONIC_ADC,
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/** and (with accumulator)*/
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MNEMONIC_AND,
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/** arithmetic shift left */
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MNEMONIC_ASL,
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/** branch on carry clear */
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MNEMONIC_BCC,
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/** branch on carry set */
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MNEMONIC_BCS,
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/** branch on equal (zero set) */
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MNEMONIC_BEQ,
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/** bit test */
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MNEMONIC_BIT,
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/** branch on minus (negative set) */
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MNEMONIC_BMI,
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/** branch on not equal (zero clear) */
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MNEMONIC_BNE,
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/** branch on plus (negative clear) */
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MNEMONIC_BPL,
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/** break / interrupt */
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MNEMONIC_BRK,
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MNEMONIC_BVC,
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MNEMONIC_BVS,
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MNEMONIC_CLC,
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MNEMONIC_CLD,
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MNEMONIC_CLI,
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MNEMONIC_CLV,
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MNEMONIC_CMP,
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MNEMONIC_CPX,
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MNEMONIC_CPY,
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MNEMONIC_DEC,
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MNEMONIC_DEX,
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MNEMONIC_DEY,
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MNEMONIC_EOR,
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MNEMONIC_INC,
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MNEMONIC_INX,
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MNEMONIC_INY,
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/** jump */
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MNEMONIC_JMP,
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/** jump subroutine */
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MNEMONIC_JSR,
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MNEMONIC_LDA,
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MNEMONIC_LDX,
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MNEMONIC_LDY,
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MNEMONIC_LSR,
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MNEMONIC_NOP,
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MNEMONIC_ORA,
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MNEMONIC_PHA,
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MNEMONIC_PHP,
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MNEMONIC_PLA,
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MNEMONIC_PLP,
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MNEMONIC_ROL,
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MNEMONIC_ROR,
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MNEMONIC_RTI,
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MNEMONIC_RTS,
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MNEMONIC_SBC,
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MNEMONIC_SEC,
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MNEMONIC_SED,
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MNEMONIC_SEI,
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MNEMONIC_STA,
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/** store X */
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MNEMONIC_STX,
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/** store Y */
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MNEMONIC_STY,
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MNEMONIC_TAX,
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MNEMONIC_TAY,
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MNEMONIC_TSX,
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MNEMONIC_TXA,
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MNEMONIC_TXS,
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MNEMONIC_TYA,
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MNEMONIC_MAX
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} Mnemonic;
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/** Return specified mnemonic string */
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const char *mnemonic_to_string(Mnemonic mnemonic);
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#endif /* !LIB_65oo2_MNEMONIC_H */
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1
lib/op.c
1
lib/op.c
|
|
@ -1,3 +1,4 @@
|
||||||
|
#include <stddef.h>
|
||||||
#include "op.h"
|
#include "op.h"
|
||||||
|
|
||||||
const uint8_t opcode_addr[OP_MAX] = {
|
const uint8_t opcode_addr[OP_MAX] = {
|
||||||
|
|
|
||||||
2
lib/op.h
2
lib/op.h
|
|
@ -5,6 +5,8 @@
|
||||||
|
|
||||||
# define OP_MAX 256
|
# define OP_MAX 256
|
||||||
|
|
||||||
|
# define IS_PREFIX(x) (x & 0x3)
|
||||||
|
|
||||||
# define OP_ADDR_IMPL 1 << 0
|
# define OP_ADDR_IMPL 1 << 0
|
||||||
# define OP_ADDR_REL 1 << 1
|
# define OP_ADDR_REL 1 << 1
|
||||||
# define OP_ADDR_IMM 1 << 2
|
# define OP_ADDR_IMM 1 << 2
|
||||||
|
|
|
||||||
|
|
@ -1,15 +1,21 @@
|
||||||
#ifndef REGISTER_H
|
#ifndef LIB_65oo2_REGISTER_H
|
||||||
# define REGISTER_H
|
# define LIB_65oo2_REGISTER_H 1
|
||||||
|
|
||||||
enum
|
typedef enum {
|
||||||
{
|
REGISTER_NONE,
|
||||||
REG_PC,
|
/** Program Counter (32bits) */
|
||||||
REG_AC,
|
REGISTER_PC,
|
||||||
REG_X,
|
/** Accumulator (32bits)*/
|
||||||
REG_Y,
|
REGISTER_AC,
|
||||||
REG_SR,
|
/** X register (32bits)*/
|
||||||
REG_SP,
|
REGISTER_X,
|
||||||
REG_MAX
|
/** Y register (32bits) */
|
||||||
};
|
REGISTER_Y,
|
||||||
|
/** Status register (8bits) */
|
||||||
|
REGISTER_SR,
|
||||||
|
/** Stack pointer (32bits) */
|
||||||
|
REGISTER_SP,
|
||||||
|
REGISTER_MAX
|
||||||
|
} Register;
|
||||||
|
|
||||||
#endif /* !REGISTER_H */
|
#endif /* !REGISTER_H */
|
||||||
|
|
|
||||||
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Reference in a new issue