65oo2/doc/isa.org

65∞2 Instruction Set Architecture

• Registers
• Control Registers
• Addressing Modes
  • Implied Addressing
  • Remative Addressing
  • Immediate Addressing
  • Absolute Addressing
• Opcodes
• Instruction encoding
  • Prefix
• Instructions Listing

Registers

PC

Program counter (32bit)

A

Accumulator (32bit)

X

X index register (32bit)

Y

Y index register (32bit)

SR

status register (8bit)

SP

stack pointer (32bit)

Status register flags

 7                0
  +-+-+-+-+-+-+-+-+
  |N|V|0|B|D|0|Z|C|
  +-+-+-+-+-+-+-+-+

N

Negative The negative flag (N) indicates the presence of a set sign bit in bit-position 31.

V

Overflow The overflow flag (V) indicates overflow with signed binary arithmetics.

B

Break

D

Decimal

Z

Zero The zero flag (Z) indicates a value of all zero bits.

C

Carry

Control Registers

Addressing Modes

Implied Addressing

Remative Addressing

Immediate Addressing

A size and a literal operand is given immediately after the instruction.

  LDA.B #7
  LDA.W #300
  LDA.L #$DEADBEEF
  LDA.SB #-5         ! sign extended
  LDA.SW #-5367      ! sign extended

Absolute Addressing

Opcodes

	-0	-1	-2	-3	-4	-5	-6	-7	-8	-9	-A	-B	-C	-D	-E	-F
0-	BRK impl	ORA X,ind		prefix				prefix	PHP impl	ORA #	ASL A			ORA abs	ASL abs
1-	BPL rel	ORA ind,Y		prefix				prefix	CLC impl	ORA abs,Y				ORA abs,X	ASL abs,X
2-	JSR abs	AND X,ind		prefix				prefix	PLP impl	AND #	ROL A		BIT abs	AND abs	ROL abs
3-	BMI rel	AND ind,Y		prefix				prefix	SEC impl	AND abs,Y				AND abs,X	ROL abs,X
4-	RTI impl	EOR X,ind		prefix				prefix	PHA impl	EOR #	LSR A		JMP abs	EOR abs	LSR abs
5-	BVC rel	EOR ind,Y		prefix				prefix	CLI impl	EOR abs,Y				EOR abs,X	LSR abs,X
6-	RTS impl	ADC X,ind	PER?	prefix				prefix	PLA impl	ADC #	ROR A		JMP ind	ADC abs	ROR abs
7-	BVS rel	ADC ind,Y		prefix				prefix	SEI impl	ADC abs,Y				ADC abs,X	ROR abs,X
8-		STA X,ind		prefix				prefix	DEY impl		TXA impl		STY abs	STA abs	STX abs
9-	BCC rel	STA ind,Y		prefix				prefix	TYA impl	STA abs,Y	TXS impl			STA abs,X
A-	LDY #	LDA X,ind	LDX #	prefix				prefix	TAY impl	LDA #	TAX impl		LDY abs	LDA abs	LDX abs
B-	BCS rel	LDA ind,Y		prefix				prefix	CLV impl	LDA abs,Y	TSX impl		LDY abs,X	LDA abs,X	LDX abs,Y
C-	CPY #	CMP X,ind		prefix				prefix	INY impl	CMP #	DEX impl		CPY abs	CMP abs	DEC abs
D-	BNE rel	CMP ind,Y		prefix				prefix	CLD impl	CMP abs,Y				CMP abs,X	DEC abs,X
E-	CPX #	SBC X,ind		prefix				prefix	INX impl	SBC #	NOP impl		CPX abs	SBC abs	INC abs
F-	BEQ rel	SBC ind,Y		prefix				prefix	SED impl	SBC abs,Y				SBC abs,X	INC abs,X

Instruction encoding

Prefix

7	6	5	4	3	2	1	0
A	A	OS	OS	0	S	1	1

OS

Size

• 00 8bit
• 01 16bit
• 10 32bit
• 11 64bit

A

Address Size

S

sign-extension

    8bits    8bits    8/16/32/64bits 
  +--------+--------+-------...---+
  | prefix | opcode | value       |
  +--------+--------+-------...---+

Instructions Listing

ADC

add with carry

AND

and (with accumulator)

ASL

arithmetic shift left

BCC

branch on carry clear

BCS

branch on carry set

BEQ

branch on equal (zero set)

BIT

bitwise test with accumulator

BMI

branch on minus

BNE

branch not equal

BPL

Branch on plus

BRK

BSR