115 lines
4.5 KiB
Org Mode
115 lines
4.5 KiB
Org Mode
#+title: 65∞2 Instruction Set Architecture
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#+author: d0p1
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** Registers
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- PC :: Program counter (32bit)
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- A :: Accumulator (32bit)
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- X :: X index register (32bit)
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- Y :: Y index register (32bit)
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- SR :: status register (8bit)
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- SP :: stack pointer (32bit)
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Status register flags
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#+begin_src
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7 0
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+-+-+-+-+-+-+-+-+
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|N|V|0|B|D|0|Z|C|
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+-+-+-+-+-+-+-+-+
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#+end_src
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- N :: Negative
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The negative flag (N) indicates the presence of a set sign bit in bit-position 31.
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- V :: Overflow
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The overflow flag (V) indicates overflow with signed binary arithmetics.
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- B :: Break
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- D :: Decimal
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- Z :: Zero
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The zero flag (Z) indicates a value of all zero bits.
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- C :: Carry
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** Control Registers
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** Addressing Modes
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*** Implied Addressing
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*** Remative Addressing
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*** Immediate Addressing
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A size and a literal operand is given immediately after the instruction.
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#+begin_src asm
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LDA.B #7
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LDA.W #300
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LDA.L #$DEADBEEF
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LDA.SB #-5 ! sign extended
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LDA.SW #-5367 ! sign extended
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#+end_src
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*** Absolute Addressing
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** Opcodes
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| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
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|----|----------|-----------|-------|--------|----|----|----|----|----------|-----------|----------|----|-----------|-----------|-----------|----|
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| 0- | BRK impl | ORA X,ind | | prefix | | | | prefix | PHP impl | ORA # | ASL A | | | ORA abs | ASL abs | |
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| 1- | BPL rel | ORA ind,Y | | prefix | | | | prefix | CLC impl | ORA abs,Y | | | | ORA abs,X | ASL abs,X | |
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| 2- | JSR abs | AND X,ind | | prefix | | | | prefix | PLP impl | AND # | ROL A | | BIT abs | AND abs | ROL abs | |
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| 3- | BMI rel | AND ind,Y | | prefix | | | | prefix | SEC impl | AND abs,Y | | | | AND abs,X | ROL abs,X | |
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| 4- | RTI impl | EOR X,ind | | prefix | | | | prefix | PHA impl | EOR # | LSR A | | JMP abs | EOR abs | LSR abs | |
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| 5- | BVC rel | EOR ind,Y | | prefix | | | | prefix | CLI impl | EOR abs,Y | | | | EOR abs,X | LSR abs,X | |
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| 6- | RTS impl | ADC X,ind | PER? | prefix | | | | prefix | PLA impl | ADC # | ROR A | | JMP ind | ADC abs | ROR abs | |
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| 7- | BVS rel | ADC ind,Y | | prefix | | | | prefix | SEI impl | ADC abs,Y | | | | ADC abs,X | ROR abs,X | |
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| 8- | | STA X,ind | | prefix | | | | prefix | DEY impl | | TXA impl | | STY abs | STA abs | STX abs | |
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| 9- | BCC rel | STA ind,Y | | prefix | | | | prefix | TYA impl | STA abs,Y | TXS impl | | | STA abs,X | | |
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| A- | LDY # | LDA X,ind | LDX # | prefix | | | | prefix | TAY impl | LDA # | TAX impl | | LDY abs | LDA abs | LDX abs | |
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| B- | BCS rel | LDA ind,Y | | prefix | | | | prefix | CLV impl | LDA abs,Y | TSX impl | | LDY abs,X | LDA abs,X | LDX abs,Y | |
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| C- | CPY # | CMP X,ind | | prefix | | | | prefix | INY impl | CMP # | DEX impl | | CPY abs | CMP abs | DEC abs | |
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| D- | BNE rel | CMP ind,Y | | prefix | | | | prefix | CLD impl | CMP abs,Y | | | | CMP abs,X | DEC abs,X | |
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| E- | CPX # | SBC X,ind | | prefix | | | | prefix | INX impl | SBC # | NOP impl | | CPX abs | SBC abs | INC abs | |
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| F- | BEQ rel | SBC ind,Y | | prefix | | | | prefix | SED impl | SBC abs,Y | | | | SBC abs,X | INC abs,X | |
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** Instruction encoding
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*** Prefix
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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|---|---|---|---|---|---|---|---|
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| A | A | OS | OS | 0 | S | 1 | 1 |
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- OS :: Size
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- 00 8bit
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- 01 16bit
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- 10 32bit
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- 11 64bit
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- A :: Address Size
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- S :: sign-extension
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#+begin_src
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8bits 8bits 8/16/32/64bits
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+--------+--------+-------...---+
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| prefix | opcode | value |
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+--------+--------+-------...---+
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#+end_src
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** Instructions Listing
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- ADC :: add with carry
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- AND :: and (with accumulator)
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- ASL :: arithmetic shift left
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- BCC :: branch on carry clear
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- BCS :: branch on carry set
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- BEQ :: branch on equal (zero set)
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- BIT :: bitwise test with accumulator
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- BMI :: branch on minus
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- BNE :: branch not equal
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- BPL :: Branch on plus
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- BRK ::
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- BSR ::
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