Update isa
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#+title: 65∞2 Instruction Set Architecture
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#+author: d0p1
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** Introduction
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- Op codes are 8 bits wide
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- The minimum addressable data is 8bits wides
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** Registers
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- PC :: Program counter (32bit)
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@ -31,13 +36,30 @@ Status register flags
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** Control Registers
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** Exception
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** Privileged Exception
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- IRQ
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- Syscall
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- Bus error
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** Non-Privileged Exception
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- undefined op code
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- undefined data type
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** Addressing Modes
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*** Implied Addressing
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*** Immediate
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*** Remative Addressing
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*** Implied
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*** Register
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*** 8 and 16 bit relative
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*** Immediate Addressing
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A size and a literal operand is given immediately after the instruction.
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@ -53,34 +75,36 @@ A size and a literal operand is given immediately after the instruction.
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** Opcodes
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| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
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|----|----------|-----------|-------|--------|----|----|----|----|----------|-----------|----------|----|-----------|-----------|-----------|----|
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| 0- | BRK impl | ORA X,ind | | prefix | | | | prefix | PHP impl | ORA # | ASL A | | | ORA abs | ASL abs | |
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| 1- | BPL rel | ORA ind,Y | | prefix | | | | prefix | CLC impl | ORA abs,Y | | | | ORA abs,X | ASL abs,X | |
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| 2- | JSR abs | AND X,ind | | prefix | | | | prefix | PLP impl | AND # | ROL A | | BIT abs | AND abs | ROL abs | |
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| 3- | BMI rel | AND ind,Y | | prefix | | | | prefix | SEC impl | AND abs,Y | | | | AND abs,X | ROL abs,X | |
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| 4- | RTI impl | EOR X,ind | | prefix | | | | prefix | PHA impl | EOR # | LSR A | | JMP abs | EOR abs | LSR abs | |
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| 5- | BVC rel | EOR ind,Y | | prefix | | | | prefix | CLI impl | EOR abs,Y | | | | EOR abs,X | LSR abs,X | |
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| 6- | RTS impl | ADC X,ind | PER? | prefix | | | | prefix | PLA impl | ADC # | ROR A | | JMP ind | ADC abs | ROR abs | |
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| 7- | BVS rel | ADC ind,Y | | prefix | | | | prefix | SEI impl | ADC abs,Y | | | | ADC abs,X | ROR abs,X | |
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| 8- | | STA X,ind | | prefix | | | | prefix | DEY impl | | TXA impl | | STY abs | STA abs | STX abs | |
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| 9- | BCC rel | STA ind,Y | | prefix | | | | prefix | TYA impl | STA abs,Y | TXS impl | | | STA abs,X | | |
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| A- | LDY # | LDA X,ind | LDX # | prefix | | | | prefix | TAY impl | LDA # | TAX impl | | LDY abs | LDA abs | LDX abs | |
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| B- | BCS rel | LDA ind,Y | | prefix | | | | prefix | CLV impl | LDA abs,Y | TSX impl | | LDY abs,X | LDA abs,X | LDX abs,Y | |
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| C- | CPY # | CMP X,ind | | prefix | | | | prefix | INY impl | CMP # | DEX impl | | CPY abs | CMP abs | DEC abs | |
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| D- | BNE rel | CMP ind,Y | | prefix | | | | prefix | CLD impl | CMP abs,Y | | | | CMP abs,X | DEC abs,X | |
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| E- | CPX # | SBC X,ind | | prefix | | | | prefix | INX impl | SBC # | NOP impl | | CPX abs | SBC abs | INC abs | |
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| F- | BEQ rel | SBC ind,Y | | prefix | | | | prefix | SED impl | SBC abs,Y | | | | SBC abs,X | INC abs,X | |
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| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
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|----+---------------+---------------+-----------+-----------+----+----+----+-----------+-------+---------------+---------+----+---------------+---------------+-----------+----|
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| 0- | *BRK* /#byte/ | *ORA* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *PHP* | *ORA* /#/ | *ASL* A | | | *ORA* /abs/ | ASL abs | |
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| 1- | *BPL* /rel/ | *ORA* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *CLC* | *ORA* /abs,Y/ | | | | *ORA* /abs,X/ | ASL abs,X | |
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| 2- | *JSR* /abs/ | *AND* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *PLP* | *AND* /#/ | *ROL* A | | *BIT* /abs/ | *AND* /abs/ | ROL abs | |
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| 3- | *BMI* /rel/ | *AND* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *SEC* | *AND* /abs,Y/ | | | | *AND* /abs,X/ | ROL abs,X | |
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| 4- | *RTI* | *EOR* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *PHA* | *EOR* /#/ | *LSR* A | | *JMP* /abs/ | *EOR* /abs/ | LSR abs | |
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| 5- | *BVC* /rel/ | *EOR* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *CLI* | *EOR* /abs,Y/ | | | | *EOR* /abs,X/ | LSR abs,X | |
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| 6- | *RTS* | *ADC* /X,ind/ | PER? | /prefix1/ | | | | /prefix1/ | *PLA* | *ADC* /#/ | *ROR* A | | *JMP* /ind/ | *ADC* /abs/ | ROR abs | |
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| 7- | *BVS* /rel/ | *ADC* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *SEI* | *ADC* /abs,Y/ | | | | *ADC* /abs,X/ | ROR abs,X | |
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| 8- | | *STA* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *DEY* | | *TXA* | | *STY* /abs/ | *STA* /abs/ | STX abs | |
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| 9- | *BCC* /rel/ | *STA* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *TYA* | *STA* /abs,Y/ | *TXS* | | | *STA* /abs,X/ | | |
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| A- | *LDY* /#/ | *LDA* /X,ind/ | *LDX* /#/ | /prefix1/ | | | | /prefix1/ | *TAY* | *LDA* /#/ | *TAX* | | *LDY* /abs/ | *LDA* /abs/ | LDX abs | |
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| B- | *BCS* /rel/ | *LDA* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *CLV* | *LDA* /abs,Y/ | *TSX* | | *LDY* /abs,X/ | *LDA* /abs,X/ | LDX abs,Y | |
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| C- | *CPY* /#/ | *CMP* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *INY* | *CMP* /#/ | *DEX* | | *CPY* /abs/ | *CMP* /abs/ | DEC abs | |
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| D- | *BNE* /rel/ | *CMP* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *CLD* | *CMP* /abs,Y/ | | | | *CMP* /abs,X/ | DEC abs,X | |
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| E- | *CPX* /#/ | *SBC* /X,ind/ | | /prefix1/ | | | | /prefix1/ | *INX* | *SBC* /#/ | *NOP* | | *CPX* /abs/ | *SBC* /abs/ | INC abs | |
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| F- | *BEQ* /rel/ | *SBC* /ind,Y/ | | /prefix1/ | | | | /prefix1/ | *SED* | *SBC* /abs,Y/ | | | | *SBC* /abs,X/ | INC abs,X | |
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** Instruction encoding
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*** Prefix
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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|---|---|---|---|---|---|---|---|
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**** Prefix 1
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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|---+---+----+----+---+---+---+---|
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| A | A | OS | OS | 0 | S | 1 | 1 |
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- OS :: Size
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- OS :: Operand Size
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- 00 8bit
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- 01 16bit
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- 10 32bit
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@ -90,7 +114,7 @@ A size and a literal operand is given immediately after the instruction.
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#+begin_src
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8bits 8bits 8/16/32/64bits
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8bits 8bits 8/16/32/64bits
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+--------+--------+-------...---+
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| prefix | opcode | value |
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+--------+--------+-------...---+
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@ -101,7 +125,7 @@ A size and a literal operand is given immediately after the instruction.
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** Instructions Listing
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- ADC :: add with carry
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- AND :: and (with accumulator)
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- AND :: bitwise and with accumulator
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- ASL :: arithmetic shift left
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- BCC :: branch on carry clear
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- BCS :: branch on carry set
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@ -109,6 +133,18 @@ A size and a literal operand is given immediately after the instruction.
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- BIT :: bitwise test with accumulator
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- BMI :: branch on minus
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- BNE :: branch not equal
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- BPL :: Branch on plus
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- BRK ::
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- BSR ::
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- BPL :: branch on plus
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- BRK :: break / interrupt
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- BVC :: branch on overflow clear
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- BVS :: branch on overflow set
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- CLC :: clear carry
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- CLD :: clear decimal
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- CLI :: disable interrupt
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- CLV :: clear overflow
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** Credits
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- [[http://www.6502.org/users/andre/65k/index.html][The 65k Project (André Fachat)]]
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- [[https://web.archive.org/web/20221029042214if_/http://archive.6502.org/datasheets/mos_65e4_microprocessor_final_design_spec_may_10_1982.pdf][mos65e4]]
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- [[http://www.mirkosoft.sk/65832.html]][WDC 65832]
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