4.7 KiB
4.7 KiB
65∞2 Instruction Set Architecture
Registers
- PC
- Program counter (32bit)
- AC
- Accumulator (32bit)
- X
- X register (32bit)
- Y
- Y register (32bit)
- SR
- status register (32bit)
- SP
- stack pointer (32bit)
Status register flags
31 0
+------ .... ----+-+-+-+-+-+-+-+-+
| |N|V| |B|D|I|Z|C|
+------ .... ----+-+-+-+-+-+-+-+-+
- N
- Negative The negative flag (N) indicates the presence of a set sign bit in bit-position 31.
- V
- Overflow The overflow flag (V) indicates overflow with signed binary arithmetics.
- B
- Break
- D
- Decimal
- I
- Interrupt
- Z
- Zero The zero flag (Z) indicates a value of all zero bits.
- C
- Carry
Addressing Modes
Implied Addressing
Remative Addressing
Immediate Addressing
A size and a literal operand is given immediately after the instruction.
LDA.B #7
LDA.W #300
LDA.L #$DEADBEEF
LDA.SB #-5 ! sign extended
LDA.SW #-5367 ! sign extended
Absolute Addressing
Opcodes
+----+----------+-----------+-------+----+-----------+-----------+-----------+----+----------+-----------+----------+----+-----------+-----------+-----------+----+
| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
+----+----------+-----------+-------+----+-----------+-----------+-----------+----+----------+-----------+----------+----+-----------+-----------+-----------+----+
| 0- | BRK impl | ORA X,ind | | | | ORA zpg | ASL zpg | | PHP impl | ORA # | ASL A | | | ORA abs | ASL abs | |
| 1- | BPL rel | ORA ind,Y | | | | ORA zpg,X | ASL zpg,X | | CLC impl | ORA abs,Y | | | | ORA abs,X | ASL abs,X | |
| 2- | JSR abs | AND X,ind | | | BIT zpg | AND zpg | ROL zpg | | PLP impl | AND # | ROL A | | BIT abs | AND abs | ROL abs | |
| 3- | BMI rel | AND ind,Y | | | | AND zpg,X | ROL zpg,X | | SEC impl | AND abs,Y | | | | AND abs,X | ROL abs,X | |
| 4- | RTI impl | EOR X,ind | | | | EOR zpg | LSR zpg | | PHA impl | EOR # | LSR A | | JMP abs | EOR abs | LSR abs | |
| 5- | BVC rel | EOR ind,Y | | | | EOR zpg,X | LSR zpg,X | | CLI impl | EOR abs,Y | | | | EOR abs,X | LSR abs,X | |
| 6- | RTS impl | ADC X,ind | | | | ADC zpg | ROR zpg | | PLA impl | ADC # | ROR A | | JMP ind | ADC abs | ROR abs | |
| 7- | BVS rel | ADC ind,Y | | | | ADC zpg,X | ROR zpg,X | | SEI impl | ADC abs,Y | | | | ADC abs,X | ROR abs,X | |
| 8- | | STA X,ind | | | STY zpg | STA zpg | STX zpg | | DEY impl | | TXA impl | | STY abs | STA abs | STX abs | |
| 9- | BCC rel | STA ind,Y | | | STY zpg,X | STA zpg,X | STX zpg,Y | | TYA impl | STA abs,Y | TXS impl | | | STA abs,X | | |
| A- | LDY # | LDA X,ind | LDX # | | LDY zpg | LDA zpg | LDX zpg | | TAY impl | LDA # | TAX impl | | LDY abs | LDA abs | LDX abs | |
| B- | BCS rel | LDA ind,Y | | | LDY zpg,X | LDA zpg,X | LDX zpg,Y | | CLV impl | LDA abs,Y | TSX impl | | LDY abs,X | LDA abs,X | LDX abs,Y | |
| C- | CPY # | CMP X,ind | | | CPY zpg | CMP zpg | DEC zpg | | INY impl | CMP # | DEX impl | | CPY abs | CMP abs | DEC abs | |
| D- | BNE rel | CMP ind,Y | | | | CMP zpg,X | DEC zpg,X | | CLD impl | CMP abs,Y | | | | CMP abs,X | DEC abs,X | |
| E- | CPX # | SBC X,ind | | | CPX zpg | SBC zpg | INC zpg | | INX impl | SBC # | NOP impl | | CPX abs | SBC abs | INC abs | |
| F- | BEQ rel | SBC ind,Y | | | | SBC zpg,X | INC zpg,X | | SED impl | SBC abs,Y | | | | SBC abs,X | INC abs,X | |
+----+----------+-----------+-------+----+-----------+-----------+-----------+----+----------+-----------+----------+----+-----------+-----------+-----------+----+
Instruction encoding
0-7 |
---|
opcode |
0-7 | 8-21 |
---|---|
opcode | relative addr |
0-7 | 8-15 | 16-X |
---|---|---|
opcode | attr | value |