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Corrects order of UART RX/TX interrupt enable bits

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(per http://byterunner.com/16550.html and manually tested in qemu bare metal echo)
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Matt Harvey 2020-09-14 14:49:57 -07:00 committed by GitHub
parent 79899c7479
commit 6781ac0036
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1 changed files with 2 additions and 2 deletions
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4
kernel/uart.c
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@ -22,8 +22,8 @@
#define RHR 0 // receive holding register (for input bytes) #define RHR 0 // receive holding register (for input bytes)
#define THR 0 // transmit holding register (for output bytes) #define THR 0 // transmit holding register (for output bytes)
#define IER 1 // interrupt enable register #define IER 1 // interrupt enable register
#define IER_TX_ENABLE (1<<0) #define IER_RX_ENABLE (1<<0)
#define IER_RX_ENABLE (1<<1) #define IER_TX_ENABLE (1<<1)
#define FCR 2 // FIFO control register #define FCR 2 // FIFO control register
#define FCR_FIFO_ENABLE (1<<0) #define FCR_FIFO_ENABLE (1<<0)
#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs #define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs