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ack/mach/powerpc/as/mach3.c

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Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/*
* $Source$
* $State$
*/
/* Integer registers */
0, GPR, 0, "r0",
0, GPR, 1, "r1",
0, GPR, 1, "sp",
0, GPR, 2, "r2",
0, GPR, 2, "fp",
0, GPR, 3, "r3",
0, GPR, 4, "r4",
0, GPR, 5, "r5",
0, GPR, 6, "r6",
0, GPR, 7, "r7",
0, GPR, 8, "r8",
0, GPR, 9, "r9",
0, GPR, 10, "r10",
0, GPR, 11, "r11",
0, GPR, 12, "r12",
0, GPR, 13, "r13",
0, GPR, 14, "r14",
0, GPR, 15, "r15",
0, GPR, 16, "r16",
0, GPR, 17, "r17",
0, GPR, 18, "r18",
0, GPR, 19, "r19",
0, GPR, 20, "r20",
0, GPR, 21, "r21",
0, GPR, 22, "r22",
0, GPR, 23, "r23",
0, GPR, 24, "r24",
0, GPR, 25, "r25",
0, GPR, 26, "r26",
0, GPR, 27, "r27",
0, GPR, 28, "r28",
0, GPR, 29, "r29",
0, GPR, 30, "r30",
0, GPR, 31, "r31",
/* Floating-point registers */
0, FPR, 0, "f0",
0, FPR, 1, "f1",
0, FPR, 2, "f2",
0, FPR, 3, "f3",
0, FPR, 4, "f4",
0, FPR, 5, "f5",
0, FPR, 6, "f6",
0, FPR, 7, "f7",
0, FPR, 8, "f8",
0, FPR, 9, "f9",
0, FPR, 10, "f10",
0, FPR, 11, "f11",
0, FPR, 12, "f12",
0, FPR, 13, "f13",
0, FPR, 14, "f14",
0, FPR, 15, "f15",
0, FPR, 16, "f16",
0, FPR, 17, "f17",
0, FPR, 18, "f18",
0, FPR, 19, "f19",
0, FPR, 20, "f20",
0, FPR, 21, "f21",
0, FPR, 22, "f22",
0, FPR, 23, "f23",
0, FPR, 24, "f24",
0, FPR, 25, "f25",
0, FPR, 26, "f26",
0, FPR, 27, "f27",
0, FPR, 28, "f28",
0, FPR, 29, "f29",
0, FPR, 30, "f30",
0, FPR, 31, "f31",
/* Special registers */
0, SPR, 32, "xer",
0, SPR, 256, "lr",
0, SPR, 288, "ctr",
/* Condition registers */
0, CR, 0, "cr0",
0, CR, 1, "cr1",
0, CR, 2, "cr2",
0, CR, 3, "cr3",
0, CR, 4, "cr4",
0, CR, 5, "cr5",
0, CR, 6, "cr6",
0, CR, 7, "cr7",
/* Condition code flag */
0, C, 0, ".",
/* Special instructions */
Rename our pseudo-opcode 'la' to 'li32'. GNU as has "la %r4,8(%r3)" as an alias for "addi %r4,%r3,8", meaning to load the address of the thing at 8(%r3). Our 'la', now 'li32', makes an addis/ori pair to load an immediate 32-bit value. For example, "li32 r4,23456789" loads a big number.
2016-09-18 21:03:23 +00:00
0, OP_LI32, 0, "li32",
Turns out Apple's hi16/ha16 exactly match my ha16/has16, so renamed accordingly. (Memo to self: read the docs *before* doing the work.)
2017-01-15 10:59:33 +00:00
0, OP_HI, 0, "hi16",
0, OP_HA, 0, "ha16",
Update the hi/lo syntax to be a bit more standard.
2017-01-15 09:21:02 +00:00
0, OP_LO, 0, "lo16",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* The next page numbers are from PowerPC User Instruction Set
* Architecture, Book I, Version 2.01.
*/
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Branch processor instructions (page 20) */
0, OP_LIL, 18<<26 | 0<<1 | 0<<0, "b",
0, OP_LIA, 18<<26 | 1<<1 | 0<<0, "ba",
0, OP_LIL, 18<<26 | 0<<1 | 1<<0, "bl",
0, OP_LIA, 18<<26 | 1<<1 | 1<<0, "bla",
0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 0<<0, "bc",
0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 0<<0, "bca",
0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 1<<0, "bcl",
0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 1<<0, "bcla",
0, OP_BO_BI_BH, 19<<26 | 16<<1 | 0<<0, "bclr",
0, OP_BO_BI_BH, 19<<26 | 16<<1 | 1<<0, "bclrl",
0, OP_BO_BI_BH, 19<<26 | 528<<1 | 0<<0, "bcctr",
0, OP_BO_BI_BH, 19<<26 | 528<<1 | 1<<0, "bcctrl",
0, OP_LEV, 17<<26 | 1<<1, "sc",
0, OP_BT_BA_BB, 19<<26 | 257<<1, "crand",
0, OP_BT_BA_BB, 19<<26 | 449<<1, "cror",
0, OP_BT_BA_BB, 19<<26 | 193<<1, "crxor",
0, OP_BT_BA_BB, 19<<26 | 225<<1, "crnand",
0, OP_BT_BA_BB, 19<<26 | 33<<1, "crnor",
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_BT_BA_BB, 19<<26 | 289<<1, "creqv",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
0, OP_BT_BA_BB, 19<<26 | 129<<1, "crandc",
0, OP_BT_BA_BB, 19<<26 | 417<<1, "crorc",
0, OP_BF_BFA, 19<<26 | 0<<1, "mcrf",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended mnemonics for bc, bcctr, bclr (page 144) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 0<<0, "bctr",
0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 1<<0, "bctrl",
0, OP_BDL, 16<<26 | 16<<21 | 0<<1 | 0<<0, "bdnz",
0, OP_BDA, 16<<26 | 16<<21 | 1<<1 | 0<<0, "bdnza",
0, OP_BH, 19<<26 | 16<<21 | 16<<1 | 0<<0, "bdnzlr",
0, OP_BDL, 16<<26 | 16<<21 | 0<<1 | 1<<0, "bdnzl",
0, OP_BDA, 16<<26 | 16<<21 | 1<<1 | 1<<0, "bdnzla",
0, OP_BH, 19<<26 | 16<<21 | 16<<1 | 1<<0, "bdnzlrl",
0, OP_BI_BDL, 16<<26 | 0<<21 | 0<<1 | 0<<0, "bdnzf",
0, OP_BI_BDA, 16<<26 | 0<<21 | 1<<1 | 0<<0, "bdnzfa",
0, OP_BI_BH, 19<<26 | 0<<21 | 16<<1 | 0<<0, "bdnzflr",
0, OP_BI_BDL, 16<<26 | 0<<21 | 0<<1 | 1<<0, "bdnzfl",
0, OP_BI_BDA, 16<<26 | 0<<21 | 1<<1 | 1<<0, "bdnzfla",
0, OP_BI_BH, 19<<26 | 0<<21 | 16<<1 | 1<<0, "bdnzflrl",
0, OP_BI_BDL, 16<<26 | 8<<21 | 0<<1 | 0<<0, "bdnzt",
0, OP_BI_BDA, 16<<26 | 8<<21 | 1<<1 | 0<<0, "bdnzta",
0, OP_BI_BH, 19<<26 | 8<<21 | 16<<1 | 0<<0, "bdnztlr",
0, OP_BI_BDL, 16<<26 | 8<<21 | 0<<1 | 1<<0, "bdnztl",
0, OP_BI_BDA, 16<<26 | 8<<21 | 1<<1 | 1<<0, "bdnztla",
0, OP_BI_BH, 19<<26 | 8<<21 | 16<<1 | 1<<0, "bdnztlrl",
0, OP_BDL, 16<<26 | 18<<21 | 0<<1 | 0<<0, "bdz",
0, OP_BDA, 16<<26 | 18<<21 | 1<<1 | 0<<0, "bdza",
0, OP_BH, 19<<26 | 18<<21 | 16<<1 | 0<<0, "bdzlr",
0, OP_BDL, 16<<26 | 18<<21 | 0<<1 | 1<<0, "bdzl",
0, OP_BDA, 16<<26 | 18<<21 | 1<<1 | 1<<0, "bdzla",
0, OP_BH, 19<<26 | 18<<21 | 16<<1 | 1<<0, "bdzlrl",
0, OP_BI_BDL, 16<<26 | 2<<21 | 0<<1 | 0<<0, "bdzf",
0, OP_BI_BDA, 16<<26 | 2<<21 | 1<<1 | 0<<0, "bdzfa",
0, OP_BI_BH, 19<<26 | 2<<21 | 16<<1 | 0<<0, "bdzflr",
0, OP_BI_BDL, 16<<26 | 2<<21 | 0<<1 | 1<<0, "bdzfl",
0, OP_BI_BDA, 16<<26 | 2<<21 | 1<<1 | 1<<0, "bdzfla",
0, OP_BI_BH, 19<<26 | 2<<21 | 16<<1 | 1<<0, "bdzflrl",
0, OP_BI_BDL, 16<<26 | 10<<21 | 0<<1 | 0<<0, "bdzt",
0, OP_BI_BDA, 16<<26 | 10<<21 | 1<<1 | 0<<0, "bdzta",
0, OP_BI_BH, 19<<26 | 10<<21 | 16<<1 | 0<<0, "bdztlr",
0, OP_BI_BDL, 16<<26 | 10<<21 | 0<<1 | 1<<0, "bdztl",
0, OP_BI_BDA, 16<<26 | 10<<21 | 1<<1 | 1<<0, "bdztla",
0, OP_BI_BH, 19<<26 | 10<<21 | 16<<1 | 1<<0, "bdztlrl",
0, OP_BI_BDL, 16<<26 | 4<<21 | 0<<1 | 0<<0, "bf",
0, OP_BI_BDA, 16<<26 | 4<<21 | 1<<1 | 0<<0, "bfa",
0, OP_BI_BH, 19<<26 | 4<<21 | 528<<1 | 0<<0, "bfctr",
0, OP_BI_BH, 19<<26 | 4<<21 | 528<<1 | 1<<0, "bfctrl",
0, OP_BI_BDL, 16<<26 | 4<<21 | 0<<1 | 1<<0, "bfl",
0, OP_BI_BDA, 16<<26 | 4<<21 | 0<<1 | 1<<0, "bfla",
0, OP_BI_BH, 19<<26 | 4<<21 | 16<<1 | 0<<0, "bflr",
0, OP_BI_BH, 19<<26 | 4<<21 | 16<<1 | 1<<0, "bflrl",
0, OP_BH, 19<<26 | 20<<21 | 16<<1 | 0<<0, "blr",
0, OP_BH, 19<<26 | 20<<21 | 16<<1 | 1<<0, "blrl",
0, OP_BI_BDL, 16<<26 | 12<<21 | 0<<1 | 0<<0, "bt",
0, OP_BI_BDA, 16<<26 | 12<<21 | 1<<1 | 0<<0, "bta",
0, OP_BI_BH, 19<<26 | 12<<21 | 528<<1 | 0<<0, "btctr",
0, OP_BI_BH, 19<<26 | 12<<21 | 528<<1 | 1<<0, "btctrl",
0, OP_BI_BDL, 16<<26 | 12<<21 | 0<<1 | 1<<0, "btl",
0, OP_BI_BDA, 16<<26 | 12<<21 | 0<<1 | 1<<0, "btla",
0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 0<<0, "btlr",
0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 1<<0, "btlrl",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m with condition in BI (page 146) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_BICR_BDL, 16<<26 | 12<<21 | 2<<16 | 0<<1 | 0<<0, "beq",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 2<<16 | 1<<1 | 0<<0, "beqa",
0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 528<<1 | 0<<0, "beqctr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 528<<1 | 1<<0, "beqctrl",
0, OP_BICR_BDL, 16<<26 | 12<<21 | 2<<16 | 0<<1 | 1<<0, "beql",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 2<<16 | 1<<1 | 1<<0, "beqla",
0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 16<<1 | 0<<0, "beqlr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 16<<1 | 1<<0, "beqlrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 0<<0, "bge",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 0<<0, "bgea",
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 0<<0, "bgectr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 1<<0, "bgectrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 1<<0, "bgel",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 1<<0, "bgela",
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 0<<0, "bgelr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 1<<0, "bgelrl",
0, OP_BICR_BDL, 16<<26 | 12<<21 | 1<<16 | 0<<1 | 0<<0, "bgt",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 1<<16 | 1<<1 | 0<<0, "bgta",
0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 528<<1 | 0<<0, "bgtctr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 528<<1 | 1<<0, "bgtctrl",
0, OP_BICR_BDL, 16<<26 | 12<<21 | 1<<16 | 0<<1 | 1<<0, "bgtl",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 1<<16 | 1<<1 | 1<<0, "bgtla",
0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 16<<1 | 0<<0, "bgtlr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 16<<1 | 1<<0, "bgtlrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 0<<0, "ble",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 0<<0, "blea",
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 0<<0, "blectr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 1<<0, "blectrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 1<<0, "blel",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 1<<0, "blela",
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 0<<0, "blelr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 1<<0, "blelrl",
0, OP_BICR_BDL, 16<<26 | 12<<21 | 0<<16 | 0<<1 | 0<<0, "blt",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 0<<16 | 1<<1 | 0<<0, "blta",
0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 528<<1 | 0<<0, "bltctr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 528<<1 | 1<<0, "bltctrl",
0, OP_BICR_BDL, 16<<26 | 12<<21 | 0<<16 | 0<<1 | 1<<0, "bltl",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 0<<16 | 1<<1 | 1<<0, "bltla",
0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 16<<1 | 0<<0, "bltlr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 16<<1 | 1<<0, "bltlrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 2<<16 | 0<<1 | 0<<0, "bne",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 2<<16 | 1<<1 | 0<<0, "bnea",
0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 528<<1 | 0<<0, "bnectr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 528<<1 | 1<<0, "bnectrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 2<<16 | 0<<1 | 1<<0, "bnel",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 2<<16 | 1<<1 | 1<<0, "bnela",
0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 16<<1 | 0<<0, "bnelr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 16<<1 | 1<<0, "bnelrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 0<<0, "bng",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 0<<0, "bnga",
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 0<<0, "bngctr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 1<<0, "bngctrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 1<<0, "bngl",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 1<<0, "bngla",
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 0<<0, "bnglr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 1<<0, "bnglrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 0<<0, "bnl",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 0<<0, "bnla",
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 0<<0, "bnlctr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 1<<0, "bnlctrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 1<<0, "bnll",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 1<<0, "bnlla",
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 0<<0, "bnllr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 1<<0, "bnllrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 0<<0, "bns",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 0<<0, "bnsa",
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 0<<0, "bnsctr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 1<<0, "bnsctrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 1<<0, "bnsl",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 1<<0, "bnsla",
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 0<<0, "bnslr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 1<<0, "bnslrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 0<<0, "bnu",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 0<<0, "bnua",
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 0<<0, "bnuctr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 1<<0, "bnuctrl",
0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 1<<0, "bnul",
0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 1<<0, "bnula",
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 0<<0, "bnulr",
0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 1<<0, "bnulrl",
0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 0<<0, "bso",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 0<<0, "bsoa",
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 0<<0, "bsoctr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 1<<0, "bsoctrl",
0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 1<<0, "bsol",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 1<<0, "bsola",
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 0<<0, "bsolr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 1<<0, "bsolrl",
0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 0<<0, "bun",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 0<<0, "buna",
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 0<<0, "bunctr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 1<<0, "bunctrl",
0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 1<<0, "bunl",
0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 1<<0, "bunla",
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 0<<0, "bunlr",
0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 1<<0, "bunlrl",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m for cr logic (page 147) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_BT_BT_BT, 19<<26 | 289<<1, "crset",
0, OP_BT_BT_BT, 19<<26 | 193<<1, "crclr",
0, OP_BT_BA_BA, 19<<26 | 449<<1, "crmove",
0, OP_BT_BA_BA, 19<<26 | 33<<1, "crnot",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Fixed point instructions (page 29) */
0, OP_RT_RA_D, 34<<26, "lbz",
0, OP_RT_RA_RB, 31<<26 | 87<<1, "lbzx",
0, OP_RT_RA_D, 35<<26, "lbzu",
0, OP_RT_RA_RB, 31<<26 | 119<<1, "lbzux",
0, OP_RT_RA_D, 40<<26, "lhz",
0, OP_RT_RA_RB, 31<<26 | 279<<1, "lhzx",
0, OP_RT_RA_D, 41<<26, "lhzu",
0, OP_RT_RA_RB, 31<<26 | 311<<1, "lhzux",
0, OP_RT_RA_D, 42<<26, "lha",
0, OP_RT_RA_RB, 31<<26 | 343<<1, "lhax",
0, OP_RT_RA_D, 43<<26, "lhau",
0, OP_RT_RA_RB, 31<<26 | 375<<1, "lhaux",
0, OP_RT_RA_D, 32<<26, "lwz",
0, OP_RT_RA_RB, 31<<26 | 23<<1, "lwzx",
0, OP_RT_RA_D, 33<<26, "lwzu",
0, OP_RT_RA_RB, 31<<26 | 55<<1, "lwzux",
0, OP_RT_RA_DS, 58<<26 | 2<<0, "lwa",
0, OP_RT_RA_RB, 31<<26 | 341<<1, "lwax",
0, OP_RT_RA_RB, 31<<26 | 363<<1, "lwaux",
0, OP_RT_RA_DS, 58<<26, "ld",
0, OP_RT_RA_RB, 31<<26 | 21<<1, "ldx",
0, OP_RT_RA_DS, 58<<26 | 1<<0, "ldu",
0, OP_RT_RA_RB, 31<<26 | 53<<1, "ldux",
0, OP_RS_RA_D, 38<<26, "stb",
0, OP_RS_RA_RB, 31<<26 | 215<<1, "stbx",
0, OP_RS_RA_D, 39<<26, "stbu",
0, OP_RS_RA_RB, 31<<26 | 247<<1, "stbux",
0, OP_RS_RA_D, 44<<26, "sth",
0, OP_RS_RA_RB, 31<<26 | 407<<1, "sthx",
0, OP_RS_RA_D, 45<<26, "sthu",
0, OP_RS_RA_RB, 31<<26 | 439<<1, "sthux",
0, OP_RS_RA_D, 36<<26, "stw",
0, OP_RS_RA_RB, 31<<26 | 151<<1, "stwx",
0, OP_RS_RA_D, 37<<26, "stwu",
0, OP_RS_RA_RB, 31<<26 | 183<<1, "stwux",
0, OP_RS_RA_DS, 62<<26, "std",
0, OP_RS_RA_RB, 31<<26 | 149<<1, "stdx",
0, OP_RS_RA_DS, 62<<26 | 1<<0, "stdu",
0, OP_RS_RA_RB, 31<<26 | 181<<1, "stdux",
/* page 42 */
0, OP_RT_RA_RB, 31<<26 | 790<<1, "lhbrx",
0, OP_RT_RA_RB, 31<<26 | 534<<1, "lwbrx",
0, OP_RS_RA_RB, 31<<26 | 918<<1, "sthbrx",
0, OP_RS_RA_RB, 31<<26 | 662<<1, "stwbrx",
/* page 44 */
0, OP_RT_RA_D, 46<<26, "lmw",
0, OP_RS_RA_D, 47<<26, "stmw",
/* page 45 */
0, OP_RT_RA_NB, 31<<26 | 597<<1, "lswi",
0, OP_RT_RA_RB, 31<<26 | 533<<1, "lswx",
0, OP_RS_RA_NB, 31<<26 | 725<<1, "stswi",
0, OP_RS_RA_RB, 31<<26 | 661<<1, "stswx",
/* page 49 */
0, OP_RT_RA_SI, 14<<26, "addi",
0, OP_RT_RA_SI, 15<<26, "addis",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 266<<1, "add",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 266<<1, "addo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 40<<1, "subf",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 40<<1, "subfo",
0, OP_RT_RA_SI_addic, 12<<26, "addic", /* special case C */
0, OP_RT_RA_SI, 8<<26, "subfic",
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 10<<1, "addc",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 10<<1, "addco",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 8<<1, "subfc",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 8<<1, "subfco",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 138<<1, "adde",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 138<<1, "addeo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 136<<1, "subfe",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 136<<1, "subfeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 234<<1, "addme",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 234<<1, "addmeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 232<<1, "subfme",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 232<<1, "subfmeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 202<<1, "addze",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 202<<1, "addzeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 200<<1, "subfze",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 200<<1, "subfzeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 104<<1, "neg",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 104<<1, "nego",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m for addition (pages 153, 154) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_RT_RA_D, 14<<26, "la",
0, OP_RT_SI, 14<<26 | 0<<16, "li",
0, OP_RT_SI, 15<<26 | 0<<16, "lis",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m for subtraction (pages 147, 148) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 40<<1, "sub",
0, OP_RT_RB_RA_C, 31<<26 | 1<<10 | 40<<1, "subo",
0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 8<<1, "subc",
0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 8<<1, "subco",
0, OP_RT_RA_SI_subi, 14<<26, "subi",
0, OP_RT_RA_SI_subi, 15<<26, "subis",
0, OP_RT_RA_SI_subic, 12<<26, "subic",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* page 54 */
0, OP_RT_RA_SI, 7<<26, "mulli",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 233<<1, "mulld",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 233<<1, "mulldo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 235<<1, "mullw",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 235<<1, "mullwo",
0, OP_RT_RA_RB_C, 31<<26 | 73<<1, "mulhd",
0, OP_RT_RA_RB_C, 31<<26 | 75<<1, "mulhw",
0, OP_RT_RA_RB_C, 31<<26 | 9<<1, "mulhdu",
0, OP_RT_RA_RB_C, 31<<26 | 11<<1, "mulhwu",
/* page 56 */
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 489<<1, "divd",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 489<<1, "divdo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 491<<1, "divw",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 491<<1, "divwo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 457<<1, "divdu",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 457<<1, "divduo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 459<<1, "divwu",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 459<<1, "divwuo",
/* page 58 */
0, OP_BF_L_RA_SI, 11<<26, "cmpi",
0, OP_BF_L_RA_RB, 31<<26 | 0<<1, "cmp",
0, OP_BF_L_RA_UI, 10<<26, "cmpli",
0, OP_BF_L_RA_RB, 31<<26 | 32<<1, "cmpl",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m for comparison (page 149) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_BF_RA_SI, 11<<26 | 1<<21, "cmpdi",
0, OP_BF_RA_RB, 31<<26 | 1<<21 | 0<<1, "cmpd",
0, OP_BF_RA_UI, 10<<26 | 1<<21, "cmpldi",
0, OP_BF_RA_RB, 31<<26 | 1<<21 | 32<<1, "cmpld",
0, OP_BF_RA_SI, 11<<26 | 0<<21, "cmpwi",
0, OP_BF_RA_RB, 31<<26 | 0<<21 | 0<<1, "cmpw",
0, OP_BF_RA_UI, 10<<26 | 0<<21, "cmplwi",
0, OP_BF_RA_RB, 31<<26 | 0<<21 | 32<<1, "cmplw",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* page 60 */
0, OP_TO_RA_SI, 2<<26, "tdi",
0, OP_TO_RA_SI, 3<<26, "twi",
0, OP_TO_RA_RB, 31<<26 | 68<<1, "td",
0, OP_TO_RA_RB, 31<<26 | 4<<1, "tw",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m for traps (page 150) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_TOX_RA_RB, 31<<26 | 4<<21 | 68<<1, "tdeq",
0, OP_TOX_RA_SI, 2<<26 | 4<<21, "tdeqi",
0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 68<<1, "tdge",
0, OP_TOX_RA_SI, 2<<26 | 12<<21, "tdgei",
0, OP_TOX_RA_RB, 31<<26 | 8<<21 | 68<<1, "tdgt",
0, OP_TOX_RA_SI, 2<<26 | 8<<21, "tdgti",
0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 68<<1, "tdle",
0, OP_TOX_RA_SI, 2<<26 | 20<<21, "tdlei",
0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 68<<1, "tdlge",
0, OP_TOX_RA_SI, 2<<26 | 5<<21, "tdlgei",
0, OP_TOX_RA_RB, 31<<26 | 1<<21 | 68<<1, "tdlgt",
0, OP_TOX_RA_SI, 2<<26 | 1<<21, "tdlgti",
0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 68<<1, "tdlle",
0, OP_TOX_RA_SI, 2<<26 | 6<<21, "tdllei",
0, OP_TOX_RA_RB, 31<<26 | 2<<21 | 68<<1, "tdllt",
0, OP_TOX_RA_SI, 2<<26 | 2<<21, "tdllti",
0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 68<<1, "tdlng",
0, OP_TOX_RA_SI, 2<<26 | 6<<21, "tdlngi",
0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 68<<1, "tdlnl",
0, OP_TOX_RA_SI, 2<<26 | 5<<21, "tdlnli",
0, OP_TOX_RA_RB, 31<<26 | 16<<21 | 68<<1, "tdlt",
0, OP_TOX_RA_SI, 2<<26 | 16<<21, "tdlti",
0, OP_TOX_RA_RB, 31<<26 | 24<<21 | 68<<1, "tdne",
0, OP_TOX_RA_SI, 2<<26 | 24<<21, "tdnei",
0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 68<<1, "tdng",
0, OP_TOX_RA_SI, 2<<26 | 20<<21, "tdngi",
0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 68<<1, "tdnl",
0, OP_TOX_RA_SI, 2<<26 | 12<<21, "tdnli",
0, OP_TOX_RA_RB, 31<<26 | 31<<21 | 68<<1, "tdu",
0, OP_TOX_RA_SI, 2<<26 | 31<<21, "tdui",
0, OP, 31<<26 | 31<<21 | 4<<1, "trap",
0, OP_TOX_RA_RB, 31<<26 | 4<<21 | 4<<1, "tweq",
0, OP_TOX_RA_SI, 3<<26 | 4<<21, "tweqi",
0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 4<<1, "twge",
0, OP_TOX_RA_SI, 3<<26 | 12<<21, "twgei",
0, OP_TOX_RA_RB, 31<<26 | 8<<21 | 4<<1, "twgt",
0, OP_TOX_RA_SI, 3<<26 | 8<<21, "twgti",
0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 4<<1, "twle",
0, OP_TOX_RA_SI, 3<<26 | 20<<21, "twlei",
0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 4<<1, "twlge",
0, OP_TOX_RA_SI, 3<<26 | 5<<21, "twlgei",
0, OP_TOX_RA_RB, 31<<26 | 1<<21 | 4<<1, "twlgt",
0, OP_TOX_RA_SI, 3<<26 | 1<<21, "twlgti",
0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 4<<1, "twlle",
0, OP_TOX_RA_SI, 3<<26 | 6<<21, "twllei",
0, OP_TOX_RA_RB, 31<<26 | 2<<21 | 4<<1, "twllt",
0, OP_TOX_RA_SI, 3<<26 | 2<<21, "twllti",
0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 4<<1, "twlng",
0, OP_TOX_RA_SI, 3<<26 | 6<<21, "twlngi",
0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 4<<1, "twlnl",
0, OP_TOX_RA_SI, 3<<26 | 5<<21, "twlnli",
0, OP_TOX_RA_RB, 31<<26 | 16<<21 | 4<<1, "twlt",
0, OP_TOX_RA_SI, 3<<26 | 16<<21, "twlti",
0, OP_TOX_RA_RB, 31<<26 | 24<<21 | 4<<1, "twne",
0, OP_TOX_RA_SI, 3<<26 | 24<<21, "twnei",
0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 4<<1, "twng",
0, OP_TOX_RA_SI, 3<<26 | 20<<21, "twngi",
0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 4<<1, "twnl",
0, OP_TOX_RA_SI, 3<<26 | 12<<21, "twnli",
0, OP_TOX_RA_RB, 31<<26 | 31<<21 | 4<<1, "twu",
0, OP_TOX_RA_SI, 3<<26 | 31<<21, "twui",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* page 62 */
Swap RA and RS when assembling "and", "or", and such instructions. They must use OP_RA_RS_RB_C instead of OP_RS_RA_RB_C. The code generator often sets RS and RA to the same register, so swapping them causes no change in many programs. I also rename OP_RS_RA_UI_CC to OP_RA_RS_UI_CC, and OP_RS_RA_C to OP_RA_RS_C, because they already swap RA and RS.
2017-01-30 20:47:09 +00:00
0, OP_RA_RS_UI_CC, 28<<26, "andi", /* C compulsory */
0, OP_RA_RS_UI_CC, 29<<26, "andis", /* C compulsory */
0, OP_RA_RS_UI, 24<<26, "ori",
0, OP_RA_RS_UI, 25<<26, "oris",
0, OP_RA_RS_UI, 26<<26, "xori",
0, OP_RA_RS_UI, 27<<26, "xoris",
0, OP_RA_RS_RB_C, 31<<26 | 28<<1, "and",
0, OP_RA_RS_RB_C, 31<<26 | 444<<1, "or",
0, OP_RA_RS_RB_C, 31<<26 | 316<<1, "xor",
0, OP_RA_RS_RB_C, 31<<26 | 476<<1, "nand",
0, OP_RA_RS_RB_C, 31<<26 | 124<<1, "nor",
0, OP_RA_RS_RB_C, 31<<26 | 284<<1, "eqv",
0, OP_RA_RS_RB_C, 31<<26 | 60<<1, "andc",
0, OP_RA_RS_RB_C, 31<<26 | 412<<1, "orc",
0, OP_RA_RS_C, 31<<26 | 954<<1, "extsb",
0, OP_RA_RS_C, 31<<26 | 922<<1, "extsh",
0, OP_RA_RS_C, 31<<26 | 986<<1, "extsw",
0, OP_RA_RS_C, 31<<26 | 58<<1, "cntlzd",
0, OP_RA_RS_C, 31<<26 | 26<<1, "cntlzw",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m using logic (pages 153, 154) */
0, OP_RA_RS_RA_C, 31<<26 | 444<<1, "mr",
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP, 24<<26, "nop",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
0, OP_RA_RS_RA_C, 31<<26 | 124<<1, "not",
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* page 69 */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_RA_RS_SH6_MB6_C, 30<<26 | 0<<2, "rldicl",
0, OP_RA_RS_SH6_MB6_C, 30<<26 | 1<<2, "rldicr",
0, OP_RA_RS_SH6_MB6_C, 30<<26 | 2<<2, "rldic",
0, OP_RA_RS_SH5_MB5_ME5_C, 21<<26, "rlwinm",
0, OP_RA_RS_RB_MB6_C, 30<<26 | 8<<1, "rldcl",
0, OP_RA_RS_RB_MB6_C, 30<<26 | 9<<1, "rldcr",
0, OP_RA_RS_RB_MB5_ME5_C, 23<<26, "rlwnm",
0, OP_RA_RS_SH6_MB6_C, 30<<26 | 3<<2, "rldimi",
0, OP_RA_RS_SH5_MB5_ME5_C, 20<<26, "rlwimi",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m for doubleword rotation (page 151) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_clrlsldi, 30<<26 | 2<<2, "clrlsldi",
0, OP_clrldi, 30<<26 | 0<<2, "clrldi",
0, OP_clrrdi, 30<<26 | 1<<2, "clrrdi",
0, OP_extldi, 30<<26 | 0<<2, "extldi",
0, OP_extrdi, 30<<26 | 1<<2, "extrdi",
0, OP_insrdi, 30<<26 | 3<<2, "insrdi",
0, OP_RA_RS_RB_C, 30<<26 | MB6(0) | 8<<1, "rotld",
0, OP_RA_RS_SH6_C, 30<<26 | MB6(0) | 0<<2, "rotldi",
0, OP_rotrdi, 30<<26 | 0<<2, "rotrdi",
0, OP_sldi, 30<<26 | 1<<2, "sldi",
0, OP_srdi, 30<<26 | 0<<2, "srdi",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m for word rotation (page 152) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_clrlslwi, 21<<26, "clrlslwi",
0, OP_clrlwi, 21<<26, "clrlwi",
0, OP_clrrwi, 21<<26, "clrrwi",
0, OP_extlwi, 21<<26, "extlwi",
0, OP_extrwi, 21<<26, "extrwi",
0, OP_inslwi, 20<<26, "inslwi",
0, OP_insrwi, 20<<26, "insrwi",
0, OP_RA_RS_RB_C, 23<<26 | 0<<6 | 31<<1, "rotlw",
0, OP_RA_RS_SH5_C, 21<<26 | 0<<6 | 31<<1, "rotlwi",
0, OP_rotrwi, 21<<26, "rotrwi",
0, OP_slwi, 21<<26, "slwi",
0, OP_srwi, 21<<26, "srwi",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* page 74 */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_RA_RS_RB_C, 31<<26 | 27<<1, "sld",
0, OP_RA_RS_RB_C, 31<<26 | 24<<1, "slw",
0, OP_RA_RS_RB_C, 31<<26 | 539<<1, "srd",
0, OP_RA_RS_RB_C, 31<<26 | 536<<1, "srw",
0, OP_RA_RS_SH6_C, 31<<26 | 413<<2, "sradi",
0, OP_RA_RS_SH5_C, 31<<26 | 824<<1, "srawi",
0, OP_RA_RS_RB_C, 31<<26 | 794<<1, "srad",
0, OP_RA_RS_RB_C, 31<<26 | 792<<1, "sraw",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* page 78 */
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
0, OP_RS_SPR, 31<<26 | 467<<1, "mtspr",
0, OP_RT_SPR, 31<<26 | 339<<1, "mfspr",
0, OP_RS_FXM, 31<<26 | 0<<20 | 144<<1, "mtcrf",
0, OP_RT, 31<<26 | 0<<20 | 19<<1, "mfcr",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* extended m for special purpose registers (page 153) */
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
0, OP_RT, 31<<26 | 9<<16 | 0<<11 | 339<<1, "mfctr",
0, OP_RT, 31<<26 | 8<<16 | 0<<11 | 339<<1, "mflr",
0, OP_RT, 31<<26 | 1<<16 | 0<<11 | 339<<1, "mfxer",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
0, OP_RS, 31<<26 | 9<<16 | 0<<11 | 467<<1, "mtctr",
0, OP_RS, 31<<26 | 8<<16 | 0<<11 | 467<<1, "mtlr",
0, OP_RS, 31<<26 | 1<<16 | 0<<11 | 467<<1, "mtxer",
/* extended m for condition register (page 154) */
0, OP_RS, 31<<26 | 0<<20 | 255<<12 | 144<<1, "mtcr",
Teach the assembler about PowerPC extended mnemonics. Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Floating point instructions (page 83) */
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* page 98 */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
0, OP_FRT_RA_D, 48<<26, "lfs",
0, OP_FRT_RA_RB, 31<<26 | 535<<1, "lfsx",
0, OP_FRT_RA_D, 49<<26, "lfsu",
0, OP_FRT_RA_RB, 31<<26 | 567<<1, "lfsux",
0, OP_FRT_RA_D, 50<<26, "lfd",
0, OP_FRT_RA_RB, 31<<26 | 599<<1, "lfdx",
0, OP_FRT_RA_D, 51<<26, "lfdu",
0, OP_FRT_RA_RB, 31<<26 | 631<<1, "lfdux",
0, OP_FRS_RA_D, 52<<26, "stfs",
0, OP_FRS_RA_RB, 31<<26 | 663<<1, "stfsx",
0, OP_FRS_RA_D, 53<<26, "stfsu",
0, OP_FRS_RA_RB, 31<<26 | 695<<1, "stfsux",
0, OP_FRS_RA_D, 54<<26, "stfd",
0, OP_FRS_RA_RB, 31<<26 | 727<<1, "stfdx",
0, OP_FRS_RA_D, 55<<26, "stfdu",
0, OP_FRS_RA_RB, 31<<26 | 759<<1, "stfdux",
0, OP_FRS_RA_RB, 31<<26 | 983<<1, "stfiwx",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* page 104 */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
0, OP_FRT_FRB_C, 63<<26 | 72<<1, "fmr",
0, OP_FRT_FRB_C, 63<<26 | 40<<1, "fneg",
0, OP_FRT_FRB_C, 63<<26 | 264<<1, "fabs",
0, OP_FRT_FRB_C, 63<<26 | 136<<1, "fnabs",
0, OP_FRT_FRA_FRB_C, 63<<26 | 21<<1, "fadd",
0, OP_FRT_FRA_FRB_C, 59<<26 | 21<<1, "fadds",
0, OP_FRT_FRA_FRB_C, 63<<26 | 20<<1, "fsub",
0, OP_FRT_FRA_FRB_C, 59<<26 | 20<<1, "fsubs",
0, OP_FRT_FRA_FRC_C, 63<<26 | 25<<1, "fmul",
0, OP_FRT_FRA_FRC_C, 59<<26 | 25<<1, "fmuls",
0, OP_FRT_FRA_FRB_C, 63<<26 | 18<<1, "fdiv",
0, OP_FRT_FRA_FRB_C, 59<<26 | 18<<1, "fdivs",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 29<<1, "fmadd",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 29<<1, "fmadds",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 28<<1, "fmsub",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 28<<1, "fmsubs",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 31<<1, "fnmadd",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 31<<1, "fnmadds",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 30<<1, "fnmsub",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 30<<1, "fnmsubs",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* page 109 */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
0, OP_FRT_FRB_C, 63<<26 | 12<<1, "frsp",
0, OP_FRT_FRB_C, 63<<26 | 814<<1, "fctid",
0, OP_FRT_FRB_C, 63<<26 | 815<<1, "fctidz",
0, OP_FRT_FRB_C, 63<<26 | 14<<1, "fctiw",
0, OP_FRT_FRB_C, 63<<26 | 15<<1, "fctiwz",
0, OP_FRT_FRB_C, 63<<26 | 846<<1, "fcfid",
0, OP_BF_FRA_FRB, 63<<26 | 0<<1, "fcmpu",
0, OP_BF_FRA_FRB, 63<<26 | 32<<1, "fcmpo",
0, OP_FRT_C, 63<<26 | 583<<1, "mffs",
0, OP_BF_BFA, 63<<26 | 64<<1, "mcrfs",
0, OP_BF_U_C, 63<<26 | 134<<1, "mtfsfi",
0, OP_FLM_FRB_C, 63<<26 | 711<<1, "mtfsf",
0, OP_BT_C, 63<<26 | 70<<1, "mtfsb0",
0, OP_BT_C, 63<<26 | 38<<1, "mtfsb1",
0, OP_FRT_FRB_C, 63<<26 | 22<<1, "fsqrt",
0, OP_FRT_FRB_C, 59<<26 | 22<<1, "fsqrts",
0, OP_FRT_FRB_C, 59<<26 | 24<<1, "fres",
0, OP_FRT_FRB_C, 63<<26 | 26<<1, "frsqrte",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 23<<1, "fsel",
Add instructions like "lwarx". Extend manual. Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
2018-03-07 18:37:31 +00:00
/* Storage control instructions (Book II, page 15) */
/* Book II, page 17 */
0, OP_RA_RB, 31<<26 | 982<<1, "icbi",
0, OP_RA_RB_TH /* page 35 */, 31<<26 | 278<<1, "dcbt",
0, OP_RA_RB, 31<<26 | 246<<1, "dcbtst",
0, OP_RA_RB, 31<<26 | 1014<<1, "dcbz",
0, OP_RA_RB, 31<<26 | 54<<1, "dcbst",
0, OP_RA_RB, 31<<26 | 86<<1, "dcbf",
0, OP, 19<<26 | 150<<1, "isync",
0, OP_RT_RA_RB, 31<<26 | 20<<1, "lwarx",
0, OP_RT_RA_RB, 31<<26 | 84<<1, "ldarx",
0, OP_RS_RA_RB_CC, 31<<26 | 150<<1 | 1<<0, "stwcx",
0, OP_RS_RA_RB_CC, 31<<26 | 150<<1 | 1<<0, "stdcx",
0, OP_L, 31<<26 | 598<<1, "sync",
0, OP, 31<<26 | 1<<21 | 598<<1, "lwsync",
0, OP, 31<<26 | 2<<21 | 598<<1, "ptesync",
0, OP, 31<<26 | 854<<1, "eieio",
/* Time base (Book II, page 30) */
0, OP_RT_TBR, 31<<26 | 371<<1, "mftb",
0, OP_RT, 31<<26 | 8<<11 | 13<<16 | 371<<1, "mftbu",
/* External control (Book II, page 33) */
0, OP_RT_RA_RB, 31<<26 | 310<<1, "eciwx",
0, OP_RS_RA_RB, 31<<26 | 438<<1, "ecowx",
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