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Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
EM_WSIZE = 4
EM_PSIZE = 4
EM_BSIZE = 8 /* two words saved in call frame */
INT8 = 1 /* Size of values */
INT16 = 2
INT32 = 4
INT64 = 8
FP_OFFSET = 0 /* Offset of saved FP relative to our FP */
PC_OFFSET = 4 /* Offset of saved PC relative to our FP */
Fill in a hint for enabling the COMMENT macro. If you want to enable comments in the .s file, change #define COMMENT(n) /* comment {LABEL, n} */ to #define COMMENT(n) comment {LABEL, n}
2016-12-09 21:58:47 +00:00
#define COMMENT(n) /* comment {LABEL, n} */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
#define nicesize(x) ((x)==INT8 || (x)==INT16 || (x)==INT32 || (x)==INT64)
#define smalls(n) sfit(n, 16)
#define smallu(n) ufit(n, 16)
In powerpc table, fix macros los() and his(). Change the operator in his() from a - minus to a + plus. When los(n) becomes negative, then his(n) needs to add 0x10000, not subtract it. Also change los(n) to do the sign extension, because smalls(los(n)) should be true, not false. Also change hi(n) and lo(n) to wrap n in parentheses, as (n), because these are macros and n might still contain operators.
2016-10-15 03:59:26 +00:00
#define lo(n) ((n) & 0xFFFF)
#define hi(n) (((n)>>16) & 0xFFFF)
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Use these for instructions that treat the low half as signed --- his()
* includes a modifier to produce the correct value when the low half gets
* sign extended. Er, do make sure you load the low half second. */
In powerpc table, fix macros los() and his(). Change the operator in his() from a - minus to a + plus. When los(n) becomes negative, then his(n) needs to add 0x10000, not subtract it. Also change los(n) to do the sign extension, because smalls(los(n)) should be true, not false. Also change hi(n) and lo(n) to wrap n in parentheses, as (n), because these are macros and n might still contain operators.
2016-10-15 03:59:26 +00:00
#define los(n) (lo(n) | (((0-(lo(n)>>15)) & ~0xFFFF)))
#define his(n) ((hi(n) + (lo(n)>>15)) & 0xFFFF)
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
#define IFFALSE {CONST, 4}
#define IFTRUE {CONST, 12}
#define ALWAYS {CONST, 20}
#define DCTRZ {CONST, 34}
#define LT {CONST, 0}
#define GT {CONST, 1}
#define EQ {CONST, 2}
PROPERTIES
GPR /* any GPR */
REG /* any allocatable GPR */
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
REG_PAIR /* speed hack for sti 8 */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
FPR /* any FPR */
FREG /* any allocatable FPR */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
FSREG /* any allocatable single-precision FPR */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SPR /* any SPR */
CR /* any CR */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
GPR0 GPRSP GPRFP GPR3 GPR4 GPR5 GPR6 GPR7
GPR8 GPR9 GPR10 GPR11 GPR12 GPR13 GPR14 GPR15
GPR16 GPR17 GPR18 GPR19 GPR20 GPR21 GPR22 GPR23
GPR24 GPR25 GPR26 GPR27 GPR28 GPR29 GPR30 GPR31
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
CR0 CR1
Check in incomplete Linux PowerPC and M68K work. --HG-- branch : dtrg-experimental-powerpc
2013-05-07 23:48:48 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
FPR0 FPR1 FPR2 FPR3 FPR4 FPR5 FPR6 FPR7
FPR8 FPR9 FPR10 FPR11 FPR12 FPR13 FPR14 FPR15
FPR16 FPR17 FPR18 FPR19 FPR20 FPR21 FPR22 FPR23
FPR24 FPR25 FPR26 FPR27 FPR28 FPR29 FPR30 FPR31
Check in incomplete Linux PowerPC and M68K work. --HG-- branch : dtrg-experimental-powerpc
2013-05-07 23:48:48 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
REGISTERS
/* Reverse order to encourage ncg to allocate them from r31 down */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
R31("r31") : GPR, REG, GPR31 regvar.
R30("r30") : GPR, REG, GPR30 regvar.
R29("r29") : GPR, REG, GPR29 regvar.
R28("r28") : GPR, REG, GPR28 regvar.
R27("r27") : GPR, REG, GPR27 regvar.
R26("r26") : GPR, REG, GPR26 regvar.
R25("r25") : GPR, REG, GPR25 regvar.
R24("r24") : GPR, REG, GPR24 regvar.
R23("r23") : GPR, REG, GPR23 regvar.
R22("r22") : GPR, REG, GPR22 regvar.
R21("r21") : GPR, REG, GPR21 regvar.
R20("r20") : GPR, REG, GPR20 regvar.
R19("r19") : GPR, REG, GPR19 regvar.
R18("r18") : GPR, REG, GPR18 regvar.
R17("r17") : GPR, REG, GPR17 regvar.
R16("r16") : GPR, REG, GPR16 regvar.
R15("r15") : GPR, REG, GPR15 regvar.
R14("r14") : GPR, REG, GPR14 regvar.
R13("r13") : GPR, REG, GPR13 regvar.
R12("r12") : GPR, REG, GPR12.
R11("r11") : GPR, GPR11.
R10("r10") : GPR, REG, GPR10.
R9("r9") : GPR, REG, GPR9.
R8("r8") : GPR, REG, GPR8.
R7("r7") : GPR, REG, GPR7.
R6("r6") : GPR, REG, GPR6.
R5("r5") : GPR, REG, GPR5.
R4("r4") : GPR, REG, GPR4.
R3("r3") : GPR, REG, GPR3.
FP("fp") : GPR, GPRFP.
SP("sp") : GPR, GPRSP.
R0("r0") : GPR, GPR0.
Check in incomplete Linux PowerPC and M68K work. --HG-- branch : dtrg-experimental-powerpc
2013-05-07 23:48:48 +00:00
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
/* speed hack for sti 8 */
PAIR_R9_R10=R9+R10 : REG_PAIR.
PAIR_R7_R8=R7+R8 : REG_PAIR.
PAIR_R5_R6=R5+R6 : REG_PAIR.
PAIR_R3_R4=R3+R4 : REG_PAIR.
Remove f14 to f31 from FREG and FSREG. This would have happened later, if f14 to f31 became regvar (like r13 to r31 are now). I am doing it now because ncg is too slow for rules "with FREG FREG uses FREG". We use such rules for adf 8 and other EM instructions that operate on 2 floats. Like my last commit cfbc537, this commit speeds ncg by removing choices for register allocation.
2016-10-19 01:16:47 +00:00
/*
* F14 to F31 are reserved for regvar, if we ever implement
* it. Don't add them to FREG; the register allocator would
* be too slow.
*/
F31("f31") : FPR, FPR31.
F30("f30") : FPR, FPR30.
F29("f29") : FPR, FPR29.
F28("f28") : FPR, FPR28.
F27("f27") : FPR, FPR27.
F26("f26") : FPR, FPR26.
F25("f25") : FPR, FPR25.
F24("f24") : FPR, FPR24.
F23("f23") : FPR, FPR23.
F22("f22") : FPR, FPR22.
F21("f21") : FPR, FPR21.
F20("f20") : FPR, FPR20.
F19("f19") : FPR, FPR19.
F18("f18") : FPR, FPR18.
F17("f17") : FPR, FPR17.
F16("f16") : FPR, FPR16.
F15("f15") : FPR, FPR15.
F14("f14") : FPR, FPR14.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
F13("f13") : FPR, FREG, FPR13.
F12("f12") : FPR, FREG, FPR12.
F11("f11") : FPR, FREG, FPR11.
F10("f10") : FPR, FREG, FPR10.
F9("f9") : FPR, FREG, FPR9.
F8("f8") : FPR, FREG, FPR8.
F7("f7") : FPR, FREG, FPR7.
F6("f6") : FPR, FREG, FPR6.
F5("f5") : FPR, FREG, FPR5.
F4("f4") : FPR, FREG, FPR4.
F3("f3") : FPR, FREG, FPR3.
F2("f2") : FPR, FREG, FPR2.
F1("f1") : FPR, FREG, FPR1.
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
F0("f0") : FPR, FPR0.
FS13("f13")=F13 : FSREG.
FS12("f12")=F12 : FSREG.
FS11("f11")=F11 : FSREG.
FS10("f10")=F10 : FSREG.
FS9("f9")=F9 : FSREG.
FS8("f8")=F8 : FSREG.
FS7("f7")=F7 : FSREG.
FS6("f6")=F6 : FSREG.
FS5("f5")=F5 : FSREG.
FS4("f4")=F4 : FSREG.
FS3("f3")=F3 : FSREG.
FS2("f2")=F2 : FSREG.
FS1("f1")=F1 : FSREG.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
LR("lr") : SPR.
CTR("ctr") : SPR.
C0("cr0") : CR, CR0.
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
#define RSCRATCH R11
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
#define FSCRATCH F0
TOKENS
/* Used only in instruction descriptions (to generate the correct syntax). */
GPRINDIRECT = { GPR reg; INT off; } 4 off "(" reg ")".
Update the hi/lo syntax to be a bit more standard.
2017-01-15 09:21:02 +00:00
GPRINDIRECT_OFFSET_LO = { GPR reg; ADDR adr; } 4 "lo16[" adr "](" reg ")".
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
CONST = { INT val; } 4 val.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Primitives */
LABEL = { ADDR adr; } 4 adr.
Signed vs unsigned lower halves of powerpc fixups are now handled by having two assembler directives, ha16() and has16(), for the upper half; has16() applies the sign adjustment. .powerpcfixup is now gone, as we generate the relocation in ha*() instead. Add special logic to the linker for undoing and redoing the sign adjustment when reading/writing fixups. Tests still pass.
2017-01-15 10:51:37 +00:00
LABEL_OFFSET_HA = { ADDR adr; } 4 "ha16[" adr "]".
LABEL_OFFSET_HAS = { ADDR adr; } 4 "has16[" adr "]".
Update the hi/lo syntax to be a bit more standard.
2017-01-15 09:21:02 +00:00
LABEL_OFFSET_LO = { ADDR adr; } 4 "lo16[" adr "]".
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
LOCAL = { INT off; } 4.
/* Allows us to use regvar() to refer to registers */
GPRE = { GPR reg; } 4 reg.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
/* Constants on the stack */
CONST_N8000 = { INT val; } 4.
CONST_N7FFF_N0001 = { INT val; } 4.
CONST_0000_7FFF = { INT val; } 4.
CONST_8000 = { INT val; } 4.
CONST_8001_FFFF = { INT val; } 4.
CONST_HZ = { INT val; } 4.
CONST_HL = { INT val; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Expression partial results */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
SUM_RIS = { GPR reg; INT offhi; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SUM_RC = { GPR reg; INT off; } 4.
SUM_RR = { GPR reg1; GPR reg2; } 4.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
TRISTATE_RC_S = { GPR reg; INT val; } 4.
TRISTATE_RC_U = { GPR reg; INT val; } 4.
TRISTATE_RR_S = { GPR reg1; GPR reg2; } 4.
TRISTATE_RR_U = { GPR reg1; GPR reg2; } 4.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
TRISTATE_FF = { FPR reg1; FPR reg2; } 4.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SEX_B = { GPR reg; } 4.
SEX_H = { GPR reg; } 4.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
IND_RC_B = { GPR reg; INT off; } 4.
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
IND_RR_B = { GPR reg1; GPR reg2; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
IND_RC_H = { GPR reg; INT off; } 4.
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
IND_RR_H = { GPR reg1; GPR reg2; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
IND_RC_H_S = { GPR reg; INT off; } 4.
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
IND_RR_H_S = { GPR reg1; GPR reg2; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
IND_RC_W = { GPR reg; INT off; } 4.
IND_RR_W = { GPR reg1; GPR reg2; } 4.
IND_RC_D = { GPR reg; INT off; } 8.
IND_RR_D = { GPR reg1; GPR reg2; } 8.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
NOT_R = { GPR reg; } 4.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
AND_RR = { GPR reg1; GPR reg2; } 4.
OR_RR = { GPR reg1; GPR reg2; } 4.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
OR_RIS = { GPR reg; INT valhi; } 4.
OR_RC = { GPR reg; INT val; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
XOR_RR = { GPR reg1; GPR reg2; } 4.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
XOR_RIS = { GPR reg; INT valhi; } 4.
XOR_RC = { GPR reg; INT val; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SETS
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
/* signed 16-bit integer */
CONST2 = CONST_N8000 + CONST_N7FFF_N0001 + CONST_0000_7FFF.
/* integer that, when negated, fits signed 16-bit */
CONST2_WHEN_NEG = CONST_N7FFF_N0001 + CONST_0000_7FFF + CONST_8000.
/* unsigned 16-bit integer */
UCONST2 = CONST_0000_7FFF + CONST_8000 + CONST_8001_FFFF.
/* any constant on stack */
CONST_ALL = CONST_N8000 + CONST_N7FFF_N0001 + CONST_0000_7FFF +
CONST_8000 + CONST_8001_FFFF + CONST_HZ + CONST_HL.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SUM_ALL = SUM_RC + SUM_RR.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
TRISTATE_ALL = TRISTATE_RC_S + TRISTATE_RC_U + TRISTATE_RR_S +
TRISTATE_RR_U + TRISTATE_FF.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SEX_ALL = SEX_B + SEX_H.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
LOGICAL_ALL = NOT_R + AND_RR + OR_RR + OR_RC + XOR_RR +
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
XOR_RC.
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
/* indirect 4-byte value */
IND_ALL_W = IND_RC_W + IND_RR_W.
/* indirect 8-byte value */
Remove IND_LABEL_W and IND_LABEL_D Because li32 always loads a label into a GPR, it is sufficient to coerce LABEL to REG, then use IND_RC_W or IND_RC_D for indirection through the label.
2016-10-16 20:33:24 +00:00
IND_ALL_D = IND_RC_D + IND_RR_D.
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
/* any indirect value that fits in a GPR */
IND_ALL_BHW = IND_RC_B + IND_RR_B + IND_RC_H + IND_RR_H +
IND_RC_H_S + IND_RR_H_S + IND_ALL_W.
/* anything killed by sti (store indirect) */
MEMORY = IND_ALL_BHW + IND_ALL_D.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
OP_ALL_W = SUM_ALL + TRISTATE_ALL + SEX_ALL + LOGICAL_ALL +
IND_ALL_W.
INSTRUCTIONS
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
/* We give time as cycles of total latency from Freescale
* Semiconductor, MPC7450 RISC Microprocessor Family Reference
* Manual, Rev. 5, section 6.6.
*
* We have only 4-byte alignment for doubles; 8-byte alignment is
* optimal. We guess the misalignment penalty by adding 1 cycle to
* the cost of loading or storing a double:
* lfd lfdu lfdx: 4 -> 5
* stfd stfdu stfdx: 3 -> 4
*/
cost(4, 1) /* space, time */
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
add GPR:wo, GPR:ro, GPR:ro.
addX "add." GPR:wo, GPR:ro, GPR:ro.
addi GPR:wo, GPR:ro, CONST:ro.
Signed vs unsigned lower halves of powerpc fixups are now handled by having two assembler directives, ha16() and has16(), for the upper half; has16() applies the sign adjustment. .powerpcfixup is now gone, as we generate the relocation in ha*() instead. Add special logic to the linker for undoing and redoing the sign adjustment when reading/writing fixups. Tests still pass.
2017-01-15 10:51:37 +00:00
addis GPR:wo, GPR:ro, CONST+LABEL_OFFSET_HA+LABEL_OFFSET_HAS:ro.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
and GPR:wo, GPR:ro, GPR:ro.
andc GPR:wo, GPR:ro, GPR:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
andiX "andi." GPR:wo:cc, GPR:ro, CONST:ro.
andisX "andis." GPR:wo:cc, GPR:ro, CONST:ro.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
b LABEL:ro.
bc CONST:ro, CONST:ro, LABEL:ro.
bcctr CONST:ro, CONST:ro, CONST:ro.
bcctrl CONST:ro, CONST:ro, CONST:ro.
bclr CONST:ro, CONST:ro, CONST:ro.
bl LABEL:ro.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
cmp CR:ro, CONST:ro, GPR:ro, GPR:ro kills :cc.
cmpi CR:ro, CONST:ro, GPR:ro, CONST:ro kills :cc.
cmpl CR:ro, CONST:ro, GPR:ro, GPR:ro kills :cc.
cmpli CR:ro, CONST:ro, GPR:ro, CONST:ro kills :cc.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
divw GPR:wo, GPR:ro, GPR:ro cost(4, 23).
divwu GPR:wo, GPR:ro, GPR:ro cost(4, 23).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
eqv GPR:wo, GPR:ro, GPR:ro.
extsb GPR:wo, GPR:ro.
extsh GPR:wo, GPR:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
fadd FREG:wo, FREG:ro, FREG:ro cost(4, 5).
fadds FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5).
fcmpo CR:wo, FPR:ro, FPR:ro cost(4, 5).
fdiv FREG:wo, FREG:ro, FREG:ro cost(4, 35).
fdivs FSREG:wo, FSREG:ro, FSREG:ro cost(4, 21).
fmr FPR:wo, FPR:ro cost(4, 5).
fmr FSREG:wo, FSREG:ro cost(4, 5).
fmul FREG:wo, FREG:ro, FREG:ro cost(4, 5).
fmuls FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5).
fneg FREG:wo, FREG:ro cost(4, 5).
fneg FSREG:wo, FSREG:ro cost(4, 5).
frsp FSREG:wo, FREG:ro cost(4, 5).
fsub FREG:wo, FREG:ro, FREG:ro cost(4, 5).
fsubs FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5).
lbz GPR:wo, GPRINDIRECT:ro cost(4, 3).
lbzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
lfd FPR:wo, GPRINDIRECT:ro cost(4, 5).
lfdu FPR:wo, GPRINDIRECT:ro cost(4, 5).
lfdx FPR:wo, GPR:ro, GPR:ro cost(4, 5).
lfs FSREG:wo, GPRINDIRECT:ro cost(4, 4).
lfsu FSREG:wo, GPRINDIRECT:rw cost(4, 4).
lfsx FSREG:wo, GPR:ro, GPR:ro cost(4, 4).
lha GPR:wo, GPRINDIRECT:ro cost(4, 3).
lhax GPR:wo, GPR:ro, GPR:ro cost(4, 3).
lhz GPR:wo, GPRINDIRECT:ro cost(4, 3).
lhzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
inn on ncg now passes the CPU tests.
2016-11-20 18:35:34 +00:00
li32 GPR:wo, CONST:ro cost(8, 2).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
lwzu GPR:wo, GPRINDIRECT:ro cost(4, 3).
lwzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
Add assembler support for fixing up arbitrary oris/addi pairs of instructions; this should allow oris/lwz constant value loads, which will save an opcode.
2017-01-14 23:15:01 +00:00
lwz GPR:wo, GPRINDIRECT+GPRINDIRECT_OFFSET_LO:ro cost(4, 3).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
nand GPR:wo, GPR:ro, GPR:ro.
neg GPR:wo, GPR:ro.
nor GPR:wo, GPR:ro, GPR:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
mfcr GPR:wo cost(4,2).
mullw GPR:wo, GPR:ro, GPR:ro cost(4, 4).
mfspr GPR:wo, SPR:ro cost(4, 3).
mtspr SPR:wo, GPR:ro cost(4, 2).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
or GPR:wo, GPR:ro, GPR:ro.
orc GPR:wo, GPR:ro, GPR:ro.
Add assembler support for fixing up arbitrary oris/addi pairs of instructions; this should allow oris/lwz constant value loads, which will save an opcode.
2017-01-14 23:15:01 +00:00
ori GPR:wo, GPR:ro, CONST+LABEL_OFFSET_LO:ro.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
oris GPR:wo, GPR:ro, CONST:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
orX "or." GPR:wo:cc, GPR:ro, GPR:ro.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
rlwinm GPR:wo, GPR:ro, CONST:ro, CONST:ro, CONST:ro.
slw GPR:wo, GPR:ro, GPR:ro.
subf GPR:wo, GPR:ro, GPR:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
sraw GPR:wo, GPR:ro, GPR:ro cost(4, 2).
srawi GPR:wo, GPR:ro, CONST:ro cost(4, 2).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
srw GPR:wo, GPR:ro, GPR:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
stb GPR:ro, GPRINDIRECT:rw cost(4, 3).
stbx GPR:ro, GPR:ro, GPR:ro cost(4, 3).
stfd FPR:ro, GPRINDIRECT:rw cost(4, 4).
stfdu FPR:ro, GPRINDIRECT:rw cost(4, 4).
stfdx FPR:ro, GPR:ro, GPR:ro cost(4, 4).
stfs FSREG:ro, GPRINDIRECT:rw cost(4, 3).
stfsu FSREG:ro, GPRINDIRECT:rw cost(4, 3).
stfsx FSREG:ro, GPR:ro, GPR:ro cost(4, 3).
sth GPR:ro, GPRINDIRECT:rw cost(4, 3).
sthx GPR:ro, GPR:ro, GPR:ro cost(4, 3).
stw GPR:ro, GPRINDIRECT:rw cost(4, 3).
stwx GPR:ro, GPR:ro, GPR:ro cost(4, 3).
stwu GPR+GPRE:ro, GPRINDIRECT:rw cost(4, 3).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
xor GPR:wo, GPR:ro, GPR:ro.
xori GPR:wo, GPR:ro, CONST:ro.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
xoris GPR:wo, GPR:ro, CONST:ro.
Remove the "invalid" stacking rule. When ncg fell back on this rule, it did emit the string "invalid" in the assembly code and caused a syntax error in the assembler. Adjust the stacking rules so we can stack LOCAL, CONST, and LABEL without falling back on the "invalid" rule, and so we can stack them when we have no free register except the scratch register.
2016-09-27 20:46:11 +00:00
Add assembler support for fixing up arbitrary oris/addi pairs of instructions; this should allow oris/lwz constant value loads, which will save an opcode.
2017-01-14 23:15:01 +00:00
comment "!" LABEL:ro cost(0, 0).
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
MOVES
from GPR to GPR
gen
COMMENT("move GPR->GPR")
or %2, %1, %1
/* GPRE exists solely to allow us to use regvar() (which can only be used in
an expression) as a register constant. */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from GPR to GPRE
gen
COMMENT("move GPR->GPRE")
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
or %2.reg, %1, %1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Constants */
Add a move from CONST smalls(%val) to GPR. This allows 'move {CONST, $1}, R3' with a small enough $1 to emit one instruction (addi) instead of two instructions (addis, ori). The CONST token confusingly isn't in the CONST_ALL set.
2016-12-09 23:40:14 +00:00
from CONST_ALL + CONST smalls(%val) to GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
COMMENT("move CONST_ALL->GPR smalls")
addi %2, R0, {CONST, %1.val}
from CONST_ALL + CONST to GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
COMMENT("move CONST_ALL->GPR")
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
addis %2, R0, {CONST, hi(%1.val)}
ori %2, %2, {CONST, lo(%1.val)}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
/* Can't use addi %2, %2, {CONST, los(%1.val)}
* because %2 might be R0. */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from LABEL to GPR
gen
COMMENT("move LABEL->GPR")
Signed vs unsigned lower halves of powerpc fixups are now handled by having two assembler directives, ha16() and has16(), for the upper half; has16() applies the sign adjustment. .powerpcfixup is now gone, as we generate the relocation in ha*() instead. Add special logic to the linker for undoing and redoing the sign adjustment when reading/writing fixups. Tests still pass.
2017-01-15 10:51:37 +00:00
addis %2, R0, {LABEL_OFFSET_HA, %1.adr}
Add assembler support for fixing up arbitrary oris/addi pairs of instructions; this should allow oris/lwz constant value loads, which will save an opcode.
2017-01-14 23:15:01 +00:00
ori %2, %2, {LABEL_OFFSET_LO, %1.adr}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Sign extension */
from SEX_B to GPR
gen
COMMENT("move SEX_B->GPR")
extsb %2, %1.reg
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SEX_H to GPR
gen
COMMENT("move SEX_H->GPR")
extsh %2, %1.reg
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Register + something */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
from SUM_RIS to GPR
gen
COMMENT("move SUM_RIS->GPR")
addis %2, %1.reg, {CONST, %1.offhi}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SUM_RC to GPR
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
gen
COMMENT("move SUM_RC->GPR")
addi %2, %1.reg, {CONST, %1.off}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SUM_RR to GPR
gen
COMMENT("move SUM_RR->GPR")
add %2, %1.reg1, %1.reg2
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
/* Read byte */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_RC_B to GPR
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move IND_RC_B->GPR")
lbz %2, {GPRINDIRECT, %1.reg, %1.off}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from IND_RR_B to GPR
gen
COMMENT("move IND_RR_B->GPR")
lbzx %2, %1.reg1, %1.reg2
/* Write byte */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from GPR to IND_RC_B
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move GPR->IND_RC_B")
stb %1, {GPRINDIRECT, %2.reg, %2.off}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from GPR to IND_RR_B
gen
COMMENT("move GPR->IND_RR_B")
stbx %1, %2.reg1, %2.reg2
/* Read halfword (short) */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_RC_H to GPR
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move IND_RC_H->GPR")
lhz %2, {GPRINDIRECT, %1.reg, %1.off}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from IND_RR_H to GPR
gen
COMMENT("move IND_RR_H->GPR")
lhzx %2, %1.reg1, %1.reg2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_RC_H_S to GPR
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move IND_RC_H_S->GPR")
lha %2, {GPRINDIRECT, %1.reg, %1.off}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from IND_RR_H_S to GPR
gen
COMMENT("move IND_RR_H_S->GPR")
lhax %2, %1.reg1, %1.reg2
/* Write halfword */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from GPR to IND_RC_H
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move GPR->IND_RC_H")
sth %1, {GPRINDIRECT, %2.reg, %2.off}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from GPR to IND_RR_H
gen
COMMENT("move GPR->IND_RR_H")
sthx %1, %2.reg1, %2.reg2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Read word */
from IND_RC_W to GPR
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move IND_RC_W->GPR")
lwz %2, {GPRINDIRECT, %1.reg, %1.off}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_RR_W to GPR
gen
COMMENT("move IND_RR_W->GPR")
lwzx %2, %1.reg1, %1.reg2
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from IND_RC_W to FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move IND_RC_W->FSREG")
lfs %2, {GPRINDIRECT, %1.reg, %1.off}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from IND_RR_W to FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("move IND_RR_W->FSREG")
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
lfsx %2, %1.reg1, %1.reg2
Remove IND_LABEL_W and IND_LABEL_D Because li32 always loads a label into a GPR, it is sufficient to coerce LABEL to REG, then use IND_RC_W or IND_RC_D for indirection through the label.
2016-10-16 20:33:24 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Write word */
from GPR to IND_RC_W
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move GPR->IND_RC_W")
stw %1, {GPRINDIRECT, %2.reg, %2.off}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from GPR to IND_RR_W
gen
COMMENT("move GPR->IND_RR_W")
stwx %1, %2.reg1, %2.reg2
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FSREG to IND_RC_W
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move FSREG->IND_RC_W")
stfs %1, {GPRINDIRECT, %2.reg, %2.off}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FSREG to IND_RR_W
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("move FSREG->IND_RR_W")
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
stfsx %1, %2.reg1, %2.reg2
/* Read double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from IND_RC_D to FPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move IND_RC_D->FPR")
lfd %2, {GPRINDIRECT, %1.reg, %1.off}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from IND_RR_D to FPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("move IND_RR_D->FPR")
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
lfdx %2, %1.reg1, %1.reg2
/* Write double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FPR to IND_RC_D
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
COMMENT("move FPR->IND_RC_D")
stfd %1, {GPRINDIRECT, %2.reg, %2.off}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FPR to IND_RR_D
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("move FPR->IND_RR_W")
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
stfdx %1, %2.reg1, %2.reg2
Remove IND_LABEL_W and IND_LABEL_D Because li32 always loads a label into a GPR, it is sufficient to coerce LABEL to REG, then use IND_RC_W or IND_RC_D for indirection through the label.
2016-10-16 20:33:24 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Extract condition code field (actually produces (CC&3)<<2) */
from CR0 to GPR
gen
COMMENT("move CR0->GPR")
mfcr %2
rlwinm %2, %2, {CONST, 4}, {CONST, 32-4}, {CONST, 31-2}
/* Comparisons */
from TRISTATE_RR_S to CR0
gen
cmp %2, {CONST, 0}, %1.reg1, %1.reg2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from TRISTATE_RR_U to CR0
gen
cmpl %2, {CONST, 0}, %1.reg1, %1.reg2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from TRISTATE_RC_S to CR0
gen
COMMENT("move TRISTATE_RC_S->CR0 large")
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move {CONST, %1.val}, RSCRATCH
cmp %2, {CONST, 0}, %1.reg, RSCRATCH
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from TRISTATE_RC_U smallu(%val) to CR0
gen
COMMENT("move TRISTATE_RC_U->CR0 small")
cmpli %2, {CONST, 0}, %1.reg, {CONST, %1.val}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from TRISTATE_RC_U to CR0
gen
COMMENT("move TRISTATE_RC_U->CR0")
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move {CONST, %1.val}, RSCRATCH
cmpl %2, {CONST, 0}, %1.reg, RSCRATCH
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from TRISTATE_FF to CR0
gen
COMMENT("move TRISTATE_FF->CR0")
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fcmpo %2, %1.reg1, %1.reg2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from GPR to CR0
gen
COMMENT("move GPR->CR0")
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
orX RSCRATCH, %1, %1 /* alas, can't call test */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from TRISTATE_RR_S + TRISTATE_RC_S + TRISTATE_FF to GPR
gen
COMMENT("move TRISTATE_R*_S->GPR")
move %1, C0
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move C0, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
move {LABEL, ".tristate_s_table"}, %2
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
lwzx %2, %2, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from TRISTATE_RR_U + TRISTATE_RC_U to GPR
gen
COMMENT("move TRISTATE_R*_U->GPR")
move %1, C0
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move C0, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
move {LABEL, ".tristate_u_table"}, %2
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
lwzx %2, %2, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Logicals */
from NOT_R to GPR
gen
COMMENT("move NOT_R->GPR")
nor %2, %1.reg, %1.reg
from AND_RR to GPR
gen
COMMENT("move AND_RR->GPR")
and %2, %1.reg1, %1.reg2
from OR_RR to GPR
gen
COMMENT("move OR_RR->GPR")
or %2, %1.reg1, %1.reg2
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
from OR_RIS to GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
COMMENT("move OR_RIS->GPR")
oris %2, %1.reg, {CONST, %1.valhi}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from OR_RC to GPR
gen
COMMENT("move OR_RC->GPR")
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
ori %2, %1.reg, {CONST, %1.val}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from XOR_RR to GPR
gen
COMMENT("move XOR_RR->GPR")
xor %2, %1.reg1, %1.reg2
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
from XOR_RIS to GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
COMMENT("move XOR_RIS->GPR")
xoris %2, %1.reg, {CONST, %1.valhi}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from XOR_RC to GPR
gen
COMMENT("move XOR_RC->GPR")
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
xori %2, %1.reg, {CONST, %1.val}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Miscellaneous */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
from OP_ALL_W + LABEL + CONST_ALL to GPRE
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %1, %2.reg
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
TESTS
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
to test GPR
gen
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
orX RSCRATCH, %1, %1
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
STACKINGRULES
Remove the "invalid" stacking rule. When ncg fell back on this rule, it did emit the string "invalid" in the assembly code and caused a syntax error in the assembler. Adjust the stacking rules so we can stack LOCAL, CONST, and LABEL without falling back on the "invalid" rule, and so we can stack them when we have no free register except the scratch register.
2016-09-27 20:46:11 +00:00
from LOCAL to STACK
gen
COMMENT("stack LOCAL")
stwu {GPRE, regvar(%1.off)}, {GPRINDIRECT, SP, 0-4}
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
from REG to STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
COMMENT("stack REG")
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
stwu %1, {GPRINDIRECT, SP, 0-4}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
from REG_PAIR to STACK
gen
COMMENT("stack REG_PAIR")
stwu %1.2, {GPRINDIRECT, SP, 0-4}
stwu %1.1, {GPRINDIRECT, SP, 0-4}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
from CONST_ALL + LABEL to STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
COMMENT("stack CONST_ALL + LABEL")
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move %1, RSCRATCH
stwu RSCRATCH, {GPRINDIRECT, SP, 0-4}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SEX_B to STACK
gen
COMMENT("stack SEX_B")
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
extsb RSCRATCH, %1.reg
stwu RSCRATCH, {GPRINDIRECT, SP, 0-4}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SEX_H to STACK
gen
COMMENT("stack SEX_H")
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
extsh RSCRATCH, %1.reg
stwu RSCRATCH, {GPRINDIRECT, SP, 0-4}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SUM_ALL + TRISTATE_ALL + LOGICAL_ALL to STACK
gen
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
COMMENT("stack SUM_ALL + TRISTATE_ALL + LOGICAL_ALL")
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
move %1, RSCRATCH
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
stwu RSCRATCH, {GPRINDIRECT, SP, 0-4}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from IND_ALL_BHW to STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
COMMENT("stack IND_ALL_BHW")
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move %1, RSCRATCH
stwu RSCRATCH, {GPRINDIRECT, SP, 0-4}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_ALL_D to STACK
gen
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
COMMENT("stack IND_ALL_D")
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
move %1, FSCRATCH
stfdu FSCRATCH, {GPRINDIRECT, SP, 0-8}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
from FREG to STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("stack FPR")
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
stfdu %1, {GPRINDIRECT, SP, 0-8}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FSREG to STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("stack FSREG")
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
stfsu %1, {GPRINDIRECT, SP, 0-4}
Remove the "invalid" stacking rule. When ncg fell back on this rule, it did emit the string "invalid" in the assembly code and caused a syntax error in the assembler. Adjust the stacking rules so we can stack LOCAL, CONST, and LABEL without falling back on the "invalid" rule, and so we can stack them when we have no free register except the scratch register.
2016-09-27 20:46:11 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
COERCIONS
from REG
uses REG
gen
COMMENT("coerce REG->REG")
move %1, %a
yields %a
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
from CONST_ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses REG
gen
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
COMMENT("coerce CONST_ALL->REG")
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
move %1, %a
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from LABEL
uses REG
gen
COMMENT("coerce LABEL->REG")
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
move %1, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from STACK
uses REG
gen
COMMENT("coerce STACK->REG")
lwz %a, {GPRINDIRECT, SP, 0}
addi SP, SP, {CONST, 4}
yields %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
from STACK
uses REG_PAIR
gen
COMMENT("coerce STACK->REG_PAIR")
lwz %a.1, {GPRINDIRECT, SP, 0}
lwz %a.2, {GPRINDIRECT, SP, 4}
addi SP, SP, {CONST, 8}
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SEX_B
uses REG
gen
COMMENT("coerce SEX_B->REG")
extsb %a, %1.reg
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SEX_H
uses REG
gen
COMMENT("coerce SEX_H->REG")
extsh %a, %1.reg
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SUM_ALL + TRISTATE_ALL + LOGICAL_ALL
uses REG
gen
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
move %1, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FSREG
uses FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fmr %a, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
from FREG
uses FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fmr %a, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from STACK
uses FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("coerce STACK->FREG")
lfd %a, {GPRINDIRECT, SP, 0}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
addi SP, SP, {CONST, 8}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from STACK
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
uses FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("coerce STACK->FSREG")
lfs %a, {GPRINDIRECT, SP, 0}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
addi SP, SP, {CONST, 4}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
yields %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from IND_ALL_BHW
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses REG
gen
move %1, %a
yields %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_ALL_W
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
uses FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
move %1, %a
yields %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
/*
* from IND_RC_D to REG_PAIR is not possible, because
* %1.off+4 might overflow a signed 16-bit integer in
* move {IND_RC_W, %1.val, %1.off+4}, %a.2
*/
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_ALL_D
uses FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
move %1, %a
yields %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
PATTERNS
/* Intrinsics */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
pat loc $1==(0-0x8000) /* Load constant */
yields {CONST_N8000, $1}
pat loc $1>=(0-0x7FFF) && $1<=(0-1)
yields {CONST_N7FFF_N0001, $1}
pat loc $1>=0 && $1<=0x7FFF
yields {CONST_0000_7FFF, $1}
pat loc $1==0x8000
yields {CONST_8000, $1}
pat loc $1>=0x8001 && $1<=0xFFFF
yields {CONST_8001_FFFF, $1}
pat loc lo($1)==0
yields {CONST_HZ, $1}
pat loc
yields {CONST_HL, $1}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dup $1==INT32 /* Duplicate word on top of stack */
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %1 %1
Add a rule for sdl ldl $1==$2 to work around a bug. In our powerpc table, sdl fails to kill the old value of the local. This is a bug, because a later ldl can load the old value instead of the newly stored value. By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl 0", the newly added rule works around the bug, but only when the ldl is immediately after the sdl. This rule improves code that uses double-precision floating point. The output of printf("%f", 6.0) in C changes from all zero digits to "6000000" but still doesn't print the decimal point. The result of atof("-123.456") becomes correct. In startrek, I can now move the Enterprise, but I still can't fire phasers without crashing the game. We already have a rule for stl lol $1==$2. We had two copies of the rule, so I am deleting the second copy.
2016-09-30 15:50:50 +00:00
with FSREG
yields %1 %1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dup $1==INT64 /* Duplicate double-word on top of stack */
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %2 %1 %2 %1
Add a rule for sdl ldl $1==$2 to work around a bug. In our powerpc table, sdl fails to kill the old value of the local. This is a bug, because a later ldl can load the old value instead of the newly stored value. By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl 0", the newly added rule works around the bug, but only when the ldl is immediately after the sdl. This rule improves code that uses double-precision floating point. The output of printf("%f", 6.0) in C changes from all zero digits to "6000000" but still doesn't print the decimal point. The result of atof("-123.456") becomes correct. In startrek, I can now move the Enterprise, but I still can't fire phasers without crashing the game. We already have a rule for stl lol $1==$2. We had two copies of the rule, so I am deleting the second copy.
2016-09-30 15:50:50 +00:00
with FREG
yields %1 %1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat exg $1==INT32 /* Exchange top two words on stack */
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %1 %2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat stl lol $1==$2 /* Store then load local */
leaving
dup 4
stl $1
Add a rule for sdl ldl $1==$2 to work around a bug. In our powerpc table, sdl fails to kill the old value of the local. This is a bug, because a later ldl can load the old value instead of the newly stored value. By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl 0", the newly added rule works around the bug, but only when the ldl is immediately after the sdl. This rule improves code that uses double-precision floating point. The output of printf("%f", 6.0) in C changes from all zero digits to "6000000" but still doesn't print the decimal point. The result of atof("-123.456") becomes correct. In startrek, I can now move the Enterprise, but I still can't fire phasers without crashing the game. We already have a rule for stl lol $1==$2. We had two copies of the rule, so I am deleting the second copy.
2016-09-30 15:50:50 +00:00
pat sdl ldl $1==$2 /* Store then load double local */
leaving
dup 8
sdl $1
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lal sti lal loi $1==$3 && $2==$4 /* Store then load local, of a different size */
leaving
dup INT32
lal $1
sti $2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ste loe $1==$2 /* Store then load external */
leaving
dup 4
ste $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Type conversions */
pat loc loc cii loc loc cii $1==$4 && $2==$5 /* madness, generated by the C compiler */
leaving
loc $1
loc $2
cii
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cii loc loc cii $2==INT32 && $5==INT32 && $4<$2 /* madness, generated by the C compiler */
leaving
loc $4
loc $5
cii
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc ciu /* signed X -> unsigned X */
leaving
loc $1
loc $2
cuu
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cuu $1==$2 /* unsigned X -> unsigned X */
/* nop */
pat loc loc cii $1==$2 /* signed X -> signed X */
/* nop */
pat loc loc cui $1==$2 /* unsigned X -> signed X */
/* nop */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cui $1==INT8 && $2==INT32 /* unsigned char -> signed int */
/* nop */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cui $1==INT16 && $2==INT32 /* unsigned short -> signed int */
/* nop */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cii $1==INT8 && $2==INT32 /* signed char -> signed int */
with GPR
yields {SEX_B, %1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cii $1==2 && $2==4 /* signed char -> signed short */
with GPR
yields {SEX_H, %1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Local variables */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
pat lal smalls($1) /* Load address of local */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {SUM_RC, FP, $1}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
pat lal /* Load address of local */
uses REG={SUM_RIS, FP, his($1)}
yields {SUM_RC, %a, los($1)}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lol inreg($1)>0 /* Load from local */
yields {LOCAL, $1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lol /* Load from local */
leaving
lal $1
loi INT32
pat ldl /* Load double-word from local */
leaving
lal $1
loi INT32*2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat stl inreg($1)>0 /* Store to local */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_ALL + LABEL + GPR + OP_ALL_W
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
kills regvar($1), LOCAL %off==$1
gen
move %1, {GPRE, regvar($1)}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat stl /* Store to local */
leaving
lal $1
sti INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sdl /* Store double-word to local */
leaving
lal $1
sti INT32*2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lil inreg($1)>0 /* Load from indirected local */
uses REG
gen
lwz %a, {GPRINDIRECT, regvar($1), 0}
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lil /* Load from indirected local */
leaving
lol $1
loi INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sil /* Save to indirected local */
leaving
lol $1
sti INT32
Add a rule for sdl ldl $1==$2 to work around a bug. In our powerpc table, sdl fails to kill the old value of the local. This is a bug, because a later ldl can load the old value instead of the newly stored value. By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl 0", the newly added rule works around the bug, but only when the ldl is immediately after the sdl. This rule improves code that uses double-precision floating point. The output of printf("%f", 6.0) in C changes from all zero digits to "6000000" but still doesn't print the decimal point. The result of atof("-123.456") becomes correct. In startrek, I can now move the Enterprise, but I still can't fire phasers without crashing the game. We already have a rule for stl lol $1==$2. We had two copies of the rule, so I am deleting the second copy.
2016-09-30 15:50:50 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zrl /* Zero local */
leaving
loc 0
stl $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat inl /* Increment local */
leaving
lol $1
loc 1
adi 4
stl $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat del /* Decrement local */
leaving
lol $1
loc 1
sbi 4
stl $1
/* Global variables */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lpi /* Load address of external function */
leaving
lae $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lae /* Load address of external */
yields {LABEL, $1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loe /* Load word external */
leaving
lae $1
loi INT32
pat ste /* Store word external */
leaving
lae $1
sti INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lde /* Load double-word external */
leaving
lae $1
loi INT64
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sde /* Store double-word external */
leaving
lae $1
sti INT64
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zre /* Zero external */
leaving
loc 0
ste $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ine /* Increment external */
ine and ste are now declared to modify memory (preventing cached values being propagated across the modification).
2017-01-07 12:25:09 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses REG={LABEL, $1}, REG
gen
lwz %b, {GPRINDIRECT, %a, 0}
addi %b, %b, {CONST, 1}
stw %b, {GPRINDIRECT, %a, 0}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dee /* Decrement external */
ine and ste are now declared to modify memory (preventing cached values being propagated across the modification).
2017-01-07 12:25:09 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses REG={LABEL, $1}, REG
gen
lwz %b, {GPRINDIRECT, %a, 0}
addi %b, %b, {CONST, 0-1}
stw %b, {GPRINDIRECT, %a, 0}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Structures */
pat lof /* Load word offsetted */
leaving
adp $1
loi INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ldf /* Load double-word offsetted */
leaving
adp $1
loi INT64
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat stf /* Store word offsetted */
leaving
adp $1
sti INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sdf /* Store double-word offsetted */
leaving
adp $1
sti INT64
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Loads and stores */
pat loi $1==INT8 /* Load byte indirect */
with GPR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_B, %1, 0}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with SUM_RR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RR_B, %1.reg1, %1.reg2}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with SUM_RC
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_B, %1.reg, %1.off}
pat loi loc loc cii $1==INT16 && $2==INT16 && $3==INT32
/* Load half-word indirect and sign extend */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with GPR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_H_S, %1, 0}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with SUM_RR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RR_H_S, %1.reg1, %1.reg2}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with SUM_RC
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_H_S, %1.reg, %1.off}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loi $1==INT16 /* Load half-word indirect */
with GPR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_H, %1, 0}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with SUM_RR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RR_H, %1.reg1, %1.reg2}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with SUM_RC
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_H, %1.reg, %1.off}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loi $1==INT32 /* Load word indirect */
Add assembler support for fixing up arbitrary oris/addi pairs of instructions; this should allow oris/lwz constant value loads, which will save an opcode.
2017-01-14 23:15:01 +00:00
with LABEL
uses REG
gen
Signed vs unsigned lower halves of powerpc fixups are now handled by having two assembler directives, ha16() and has16(), for the upper half; has16() applies the sign adjustment. .powerpcfixup is now gone, as we generate the relocation in ha*() instead. Add special logic to the linker for undoing and redoing the sign adjustment when reading/writing fixups. Tests still pass.
2017-01-15 10:51:37 +00:00
addis %a, R0, {LABEL_OFFSET_HAS, %1.adr}
Add assembler support for fixing up arbitrary oris/addi pairs of instructions; this should allow oris/lwz constant value loads, which will save an opcode.
2017-01-14 23:15:01 +00:00
lwz %a, {GPRINDIRECT_OFFSET_LO, %a, %1.adr}
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with GPR
yields {IND_RC_W, %1, 0}
with SUM_RC
yields {IND_RC_W, %1.reg, %1.off}
with SUM_RR
yields {IND_RR_W, %1.reg1, %1.reg2}
pat loi $1==INT64 /* Load double-word indirect */
with GPR
yields {IND_RC_D, %1, 0}
with SUM_RC
yields {IND_RC_D, %1.reg, %1.off}
with SUM_RR
yields {IND_RR_D, %1.reg1, %1.reg2}
pat loi /* Load arbitrary size */
leaving
loc $1
los INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
pat los $1==INT32 /* Load arbitrary size */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with GPR3 GPR4 STACK
kills ALL
gen
bl {LABEL, ".los"}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sti $1==INT8 /* Store byte indirect */
with GPR GPR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
stb %2, {GPRINDIRECT, %1, 0}
with SUM_RR GPR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
stbx %2, %1.reg1, %1.reg2
with SUM_RC GPR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2, {IND_RC_B, %1.reg, %1.off}
with GPR SEX_B
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
stb %2.reg, {GPRINDIRECT, %1, 0}
with SUM_RR SEX_B
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
stbx %2.reg, %1.reg1, %1.reg2
with SUM_RC SEX_B
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2.reg, {IND_RC_B, %1.reg, %1.off}
pat sti $1==INT16 /* Store half-word indirect */
with GPR GPR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
sth %2, {GPRINDIRECT, %1, 0}
with SUM_RR GPR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
sthx %2, %1.reg1, %1.reg2
with SUM_RC GPR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2, {IND_RC_H, %1.reg, %1.off}
with GPR SEX_H
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
sth %2.reg, {GPRINDIRECT, %1, 0}
with SUM_RR SEX_H
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
sthx %2.reg, %1.reg1, %1.reg2
with SUM_RC SEX_H
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2.reg, {IND_RC_H, %1.reg, %1.off}
pat sti $1==INT32 /* Store word indirect */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with GPR GPR+FSREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2, {IND_RC_W, %1, 0}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with SUM_RR GPR+FSREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2, {IND_RR_W, %1.reg1, %1.reg2}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with SUM_RC GPR+FSREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2, {IND_RC_W, %1.reg, %1.off}
pat sti $1==INT64 /* Store double-word indirect */
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
with REG FREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2, {IND_RC_D, %1, 0}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with SUM_RR FREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2, {IND_RR_D, %1.reg1, %1.reg2}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with SUM_RC FREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
move %2, {IND_RC_D, %1.reg, %1.off}
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
/*
* This pattern would be too slow:
* with REG REG REG
* ncg can't handle that many registers, and would
* take about 2 seconds on each sti 8. So we use
* REG_PAIR as a speed hack for sti 8.
*/
with REG REG_PAIR
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
move %2.1, {IND_RC_W, %1, 0}
move %2.2, {IND_RC_W, %1, 4}
/*
* Next 2 patterns exist because there is no coercion
* from IND_ALL_D to REG_PAIR.
*/
with REG IND_RC_D
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
uses REG={SUM_RC, %2.reg, %2.off}, REG_PAIR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
move {IND_RC_W, %a, 0}, %b.1
move {IND_RC_W, %a, 4}, %b.2
move %b.1, {IND_RC_W, %1, 0}
move %b.2, {IND_RC_W, %1, 4}
with REG IND_RR_D
kills MEMORY
uses REG={SUM_RR, %2.reg1, %2.reg2}, REG_PAIR
gen
move {IND_RC_W, %a, 0}, %b.1
move {IND_RC_W, %a, 4}, %b.2
move %b.1, {IND_RC_W, %1, 0}
move %b.2, {IND_RC_W, %1, 4}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sti /* Store arbitrary size */
leaving
loc $1
sts INT32
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
pat sts $1==INT32 /* Store arbitrary size */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with GPR3 GPR4 STACK
kills ALL
gen
bl {LABEL, ".sts"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Arithmetic wrappers */
pat ads $1==4 /* Add var to pointer */
leaving adi $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbs $1==4 /* Subtract var from pointer */
leaving sbi $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat adp /* Add constant to pointer */
leaving
loc $1
adi 4
pat adu /* Add unsigned */
leaving
adi $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbu /* Subtract unsigned */
leaving
sbi $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat inc /* Add 1 */
leaving
loc 1
adi 4
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dec /* Subtract 1 */
leaving
loc 1
sbi 4
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc mlu $2==2 /* Unsigned multiply by constant */
leaving
loc $1
mli 4
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat mlu /* Unsigned multiply by var */
leaving
mli $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc slu /* Shift left unsigned by constant amount */
leaving
loc $1
sli $2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat slu /* Shift left unsigned by variable amount */
leaving
sli $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Word arithmetic */
pat adi $1==4 /* Add word (second + top) */
with REG REG
yields {SUM_RR, %1, %2}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST2 REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {SUM_RC, %2, %1.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG CONST2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {SUM_RC, %1, %2.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_HZ REG
uses reusing %2, REG={SUM_RIS, %2, his(%1.val)}
yields %a
with REG CONST_HZ
uses reusing %1, REG={SUM_RIS, %1, his(%2.val)}
yields %a
with CONST_ALL-CONST2-CONST_HZ REG
uses reusing %2, REG={SUM_RIS, %2, his(%1.val)}
yields {SUM_RC, %a, los(%1.val)}
with REG CONST_ALL-CONST2-CONST_HZ
uses reusing %1, REG={SUM_RIS, %1, his(%2.val)}
yields {SUM_RC, %a, los(%2.val)}
with CONST_ALL LABEL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {LABEL, %2.adr+%1.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbi $1==4 /* Subtract word (second - top) */
with REG REG
uses reusing %2, REG
gen
subf %a, %1, %2
yields %a
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST2_WHEN_NEG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {SUM_RC, %2, 0-%1.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_HZ REG
uses reusing %2, REG={SUM_RIS, %2, his(0-%1.val)}
yields %a
with CONST_ALL-CONST2_WHEN_NEG-CONST_HZ REG
uses reusing %2, REG={SUM_RIS, %2, his(0-%1.val)}
yields {SUM_RC, %a, los(0-%1.val)}
with CONST_ALL LABEL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {LABEL, %2.adr+(0-%1.val)}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ngi $1==4 /* Negate word */
with REG
uses reusing %1, REG
gen
neg %a, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat mli $1==4 /* Multiply word (second * top) */
with REG REG
uses reusing %2, REG
gen
mullw %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dvi $1==4 /* Divide word (second / top) */
with REG REG
uses reusing %2, REG
gen
divw %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dvu $1==4 /* Divide unsigned word (second / top) */
with REG REG
uses reusing %2, REG
gen
divwu %a, %2, %1
yields %a
pat rmi $1==4 /* Remainder word (second % top) */
with REG REG
uses REG
gen
divw %a, %2, %1
mullw %a, %a, %1
subf %a, %a, %2
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat rmu $1==4 /* Remainder unsigned word (second % top) */
with REG REG
uses REG
gen
divwu %a, %2, %1
mullw %a, %a, %1
subf %a, %a, %2
yields %a
pat and $1==4 /* AND word */
with GPR NOT_R
uses reusing %1, REG
gen
andc %a, %1, %2.reg
yields %a
with NOT_R GPR
uses reusing %1, REG
gen
andc %a, %2, %1.reg
yields %a
with GPR GPR
yields {AND_RR, %1, %2}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with GPR UCONST2
uses reusing %1, REG
gen
andiX %a, %1, {CONST, %2.val}
yields %a
with UCONST2 GPR
uses reusing %2, REG
gen
andiX %a, %2, {CONST, %1.val}
yields %a
with GPR CONST_HZ
uses reusing %1, REG
gen
andisX %a, %1, {CONST, hi(%2.val)}
yields %a
with CONST_HZ GPR
uses reusing %2, REG
gen
andisX %a, %2, {CONST, hi(%1.val)}
yields %a
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat and defined($1) /* AND set */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with STACK
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
move {CONST, $1}, R3
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
bl {LABEL, ".and"}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ior $1==4 /* OR word */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG NOT_R
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
orc %a, %1, %2.reg
yields %a
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with NOT_R REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
orc %a, %2, %1.reg
yields %a
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {OR_RR, %1, %2}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG UCONST2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {OR_RC, %1, %2.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with UCONST2 REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {OR_RC, %2, %1.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG CONST_HZ
uses reusing %1, REG={OR_RIS, %1, hi(%2.val)}
yields %a
with CONST_HZ REG
uses reusing %2, REG={OR_RIS, %2, hi(%1.val)}
yields %a
with REG CONST_ALL-UCONST2-CONST_HZ
uses reusing %1, REG={OR_RIS, %1, hi(%2.val)}
yields {OR_RC, %1, lo(%2.val)}
with CONST_ALL-UCONST2-CONST_HZ REG
uses reusing %2, REG={OR_RIS, %2, hi(%1.val)}
yields {OR_RC, %2, lo(%1.val)}
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat ior defined($1) /* OR set */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with STACK
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
kills ALL
gen
move {CONST, $1}, R3
bl {LABEL, ".ior"}
/* OR set (variable), used in lang/m2/libm2/LtoUset.e */
pat ior !defined($1)
with GPR3 STACK
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
bl {LABEL, ".ior"}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat xor $1==4 /* XOR word */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {XOR_RR, %1, %2}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG UCONST2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {XOR_RC, %1, %2.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with UCONST2 REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {XOR_RC, %2, %1.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG CONST_HZ
uses reusing %1, REG={XOR_RIS, %1, hi(%2.val)}
yields %a
with CONST_HZ REG
uses reusing %2, REG={XOR_RIS, %2, hi(%1.val)}
yields %a
with REG CONST_ALL-UCONST2-CONST_HZ
uses reusing %1, REG={XOR_RIS, %1, hi(%2.val)}
yields {XOR_RC, %1, lo(%2.val)}
with CONST_ALL-UCONST2-CONST_HZ REG
uses reusing %2, REG={XOR_RIS, %2, hi(%1.val)}
yields {XOR_RC, %2, lo(%1.val)}
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat xor defined($1) /* XOR set */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with STACK
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
move {CONST, $1}, R3
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
bl {LABEL, ".xor"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat com $1==INT32 /* NOT word */
with AND_RR
uses REG
gen
nand %a, %1.reg1, %1.reg2
yields %a
with OR_RR
uses REG
gen
nor %a, %1.reg1, %1.reg2
yields %a
with XOR_RR
uses REG
gen
eqv %a, %1.reg1, %1.reg2
yields %a
with GPR
yields {NOT_R, %1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat com defined($1) /* NOT set */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with STACK
gen
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
move {CONST, $1}, R3
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
bl {LABEL, ".com"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat zer $1==4 /* Push zero */
leaving
loc 0
pat zer defined($1) /* Create empty set */
with STACK
kills ALL
gen
move {CONST, $1}, R3
bl {LABEL, ".zer"}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sli $1==4 /* Shift left (second << top) */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_ALL GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
rlwinm %a, %2, {CONST, (%1.val & 0x1F)}, {CONST, 0}, {CONST, 31-(%1.val & 0x1F)}
yields %a
with GPR GPR
uses reusing %2, REG
gen
slw %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sri $1==4 /* Shift right signed (second >> top) */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_ALL GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
srawi %a, %2, {CONST, %1.val & 0x1F}
yields %a
with GPR GPR
uses reusing %2, REG
gen
sraw %a, %2, %1
yields %a
pat sru $1==4 /* Shift right unsigned (second >> top) */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_ALL GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
rlwinm %a, %2, {CONST, 32-(%1.val & 0x1F)}, {CONST, (%1.val & 0x1F)}, {CONST, 31}
yields %a
with GPR GPR
uses reusing %2, REG
gen
srw %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Arrays */
pat aar $1==INT32 /* Index array */
with GPR3 GPR4 GPR5
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
bl {LABEL, ".aar4"}
yields R3
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lae lar $2==INT32 && nicesize(rom($1, 3)) /* Load array */
leaving
lae $1
aar INT32
loi rom($1, 3)
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lar $1==INT32 /* Load array */
with GPR3 GPR4 GPR5 STACK
kills ALL
gen
bl {LABEL, ".lar4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lae sar $2==INT32 && nicesize(rom($1, 3)) /* Store array */
leaving
lae $1
aar INT32
sti rom($1, 3)
pat sar $1==INT32 /* Store array */
with GPR3 GPR4 GPR5 STACK
kills ALL
gen
bl {LABEL, ".sar4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Sets */
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat set defined($1) /* Create singleton set */
with GPR4 STACK
kills ALL
gen
move {CONST, $1}, R3
bl {LABEL, ".set"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
/* Create set (variable), used in lang/m2/libm2/LtoUset.e */
pat set !defined($1)
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
with GPR3 GPR4 STACK
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
bl {LABEL, ".set"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
pat inn defined($1) /* Test for set bit */
inn on ncg now passes the CPU tests.
2016-11-20 18:35:34 +00:00
with STACK
kills ALL
uses REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
inn on ncg now passes the CPU tests.
2016-11-20 18:35:34 +00:00
li32 %a, {CONST, $1}
stwu %a, {GPRINDIRECT, SP, 0-4}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
bl {LABEL, ".inn"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Boolean resolutions */
pat teq /* top = (top == 0) */
with TRISTATE_ALL + GPR
uses reusing %1, REG
gen
move %1, C0
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move C0, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
move {LABEL, ".teq_table"}, %a
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
lwzx %a, %a, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat tne /* top = (top != 0) */
with TRISTATE_ALL + GPR
uses reusing %1, REG
gen
move %1, C0
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move C0, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
move {LABEL, ".tne_table"}, %a
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
lwzx %a, %a, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat tlt /* top = (top < 0) */
with TRISTATE_ALL + GPR
uses reusing %1, REG
gen
move %1, C0
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move C0, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
move {LABEL, ".tlt_table"}, %a
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
lwzx %a, %a, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat tle /* top = (top <= 0) */
with TRISTATE_ALL + GPR
uses reusing %1, REG
gen
move %1, C0
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move C0, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
move {LABEL, ".tle_table"}, %a
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
lwzx %a, %a, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat tgt /* top = (top > 0) */
with TRISTATE_ALL + GPR
uses reusing %1, REG
gen
move %1, C0
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move C0, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
move {LABEL, ".tgt_table"}, %a
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
lwzx %a, %a, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
pat tge /* top = (top >= 0) */
with TRISTATE_ALL + GPR
uses reusing %1, REG
gen
move %1, C0
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move C0, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
move {LABEL, ".tge_table"}, %a
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
lwzx %a, %a, RSCRATCH
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Simple branches */
pat zeq /* Branch if signed top == 0 */
with TRISTATE_ALL+GPR STACK
gen
move %1, C0
bc IFTRUE, EQ, {LABEL, $1}
pat beq
leaving
cmi INT32
zeq $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zne /* Branch if signed top != 0 */
with TRISTATE_ALL+GPR STACK
gen
move %1, C0
bc IFFALSE, EQ, {LABEL, $1}
pat bne
leaving
cmi INT32
zne $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zgt /* Branch if signed top > 0 */
with TRISTATE_ALL+GPR STACK
gen
move %1, C0
bc IFTRUE, GT, {LABEL, $1}
pat bgt
leaving
cmi INT32
zgt $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zge /* Branch if signed top >= 0 */
with TRISTATE_ALL+GPR STACK
gen
move %1, C0
bc IFFALSE, LT, {LABEL, $1}
pat bge
leaving
cmi INT32
zge $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zlt /* Branch if signed top < 0 */
with TRISTATE_ALL+GPR STACK
gen
move %1, C0
bc IFTRUE, LT, {LABEL, $1}
pat blt
leaving
cmi INT32
zlt $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zle /* Branch if signed top >= 0 */
with TRISTATE_ALL+GPR STACK
gen
move %1, C0
bc IFFALSE, GT, {LABEL, $1}
pat ble
leaving
cmi INT32
zle $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Compare and jump */
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
pat cmi $1==INT32 /* Signed tristate compare */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_ALL GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {TRISTATE_RC_S, %2, %1.val}
with GPR GPR
yields {TRISTATE_RR_S, %2, %1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
pat cmu $1==INT32 /* Unsigned tristate compare */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_ALL GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {TRISTATE_RC_U, %2, %1.val}
with GPR GPR
yields {TRISTATE_RR_U, %2, %1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat cmp /* Compare pointers */
leaving
cmu INT32
Remove trailing whitespace in mach/powerpc/ncg/table
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Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat cms $1==INT32 /* Compare blocks (word sized) */
leaving
cmi INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat cms defined($1)
with STACK
kills ALL
gen
move {CONST, $1}, R3
bl {LABEL, ".cms"}
yields R3
Remove trailing whitespace in mach/powerpc/ncg/table
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Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Other branching and labelling */
pat lab topeltsize($1)==4 && !fallthrough($1)
gen
labeldef $1
yields R3
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lab topeltsize($1)==4 && fallthrough($1)
with GPR3
gen
labeldef $1
yields %1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lab topeltsize($1)!=4
with STACK
kills ALL
gen
labeldef $1
Remove trailing whitespace in mach/powerpc/ncg/table
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Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat bra topeltsize($1)==4 /* Unconditional jump with TOS GPRister */
with GPR3 STACK
gen
b {LABEL, $1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat bra topeltsize($1)!=4 /* Unconditional jump without TOS GPRister */
with STACK
gen
b {LABEL, $1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Miscellaneous */
pat cal /* Call procedure */
with STACK
kills ALL
gen
bl {LABEL, $1}
pat cai /* Call procedure indirect */
with GPR STACK
kills ALL
gen
mtspr CTR, %1
bcctrl ALWAYS, {CONST, 0}, {CONST, 0}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lfr $1==INT32 /* Load function result, word */
yields R3
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lfr $1==INT64 /* Load function result, double-word */
yields R4 R3
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ret $1==0 /* Return from procedure */
gen
return
b {LABEL, ".ret"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ret $1==INT32 /* Return from procedure, word */
with GPR3
gen
return
b {LABEL, ".ret"}
pat ret $1==INT64 /* Return from procedure, double-word */
with GPR3 GPR4
gen
return
b {LABEL, ".ret"}
pat blm /* Block move constant length */
with GPR GPR STACK
uses REG
gen
move {CONST, $1}, %a
stwu %a, {GPRINDIRECT, SP, 0-4}
stwu %2, {GPRINDIRECT, SP, 0-4}
stwu %1, {GPRINDIRECT, SP, 0-4}
bl {LABEL, "_memmove"}
addi SP, SP, {CONST, 12}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat bls /* Block move variable length */
with GPR GPR GPR STACK
gen
stwu %1, {GPRINDIRECT, SP, 0-4}
stwu %3, {GPRINDIRECT, SP, 0-4}
stwu %2, {GPRINDIRECT, SP, 0-4}
bl {LABEL, "_memmove"}
addi SP, SP, {CONST, 12}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat csa /* Array-lookup switch */
Made csa and csb work with mcg; adjust the libem functions and the corresponding invocation in the ncg table so the same helpers can be used for both mcg and ncg. Add a new IR opcode, FARJUMP, which jumps to a helper function but saves volatile registers.
2016-11-19 09:55:41 +00:00
with STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
b {LABEL, ".csa"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat csb /* Table-lookup switch */
Made csa and csb work with mcg; adjust the libem functions and the corresponding invocation in the ncg table so the same helpers can be used for both mcg and ncg. Add a new IR opcode, FARJUMP, which jumps to a helper function but saves volatile registers.
2016-11-19 09:55:41 +00:00
with STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
b {LABEL, ".csb"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* EM specials */
pat fil /* Set current filename */
leaving
lae $1
Remove .linenumber and .filename; use hol0 and hol0+4. We need this because some .e files in lang/ are using 'loe 0' and 'lae 4' to load the line number from hol0 and filename from hol0+4.
2016-09-30 17:40:36 +00:00
ste "hol0+4"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lin /* Set current line number */
leaving
loc $1
Remove .linenumber and .filename; use hol0 and hol0+4. We need this because some .e files in lang/ are using 'loe 0' and 'lae 4' to load the line number from hol0 and filename from hol0+4.
2016-09-30 17:40:36 +00:00
ste "hol0"
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lni /* Increment line number */
leaving
Remove .linenumber and .filename; use hol0 and hol0+4. We need this because some .e files in lang/ are using 'loe 0' and 'lae 4' to load the line number from hol0 and filename from hol0+4.
2016-09-30 17:40:36 +00:00
ine "hol0"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lim /* Load EM trap ignore mask */
leaving
lde ".ignmask"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sim /* Store EM trap ignore mask */
leaving
ste ".ignmask"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat trp /* Raise EM trap */
with GPR3
gen
bl {LABEL, ".trap"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sig /* Set trap handler */
leaving
ste ".trppc"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat rtt /* Return from trap */
leaving
ret 0
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lxl $1==0 /* Load FP */
leaving
lor 0
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lxl $1==1 /* Load caller's FP */
leaving
lxl 0
dch
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dch /* FP -> caller FP */
with GPR
uses reusing %1, REG
gen
lwz %a, {GPRINDIRECT, %1, FP_OFFSET}
yields %a
pat lpb /* Convert FP to argument address */
leaving
adp EM_BSIZE
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lxa /* Load caller's SP */
leaving
lxl $1
lpb
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat gto /* longjmp */
uses REG
gen
move {LABEL, $1}, %a
move {IND_RC_W, %a, 8}, FP
move {IND_RC_W, %a, 4}, SP
move {IND_RC_W, %a, 0}, %a
mtspr CTR, %a
bcctr ALWAYS, {CONST, 0}, {CONST, 0}
pat lor $1==0 /* Load FP */
uses REG
gen
move FP, %a
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lor $1==1 /* Load SP */
uses REG
gen
move SP, %a
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat str $1==0 /* Store FP */
with GPR
gen
move %1, FP
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat str $1==1 /* Store SP */
with GPR
gen
move %1, SP
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Fix ass to match the EM spec. The spec says, "ASS w: Adjust the stack pointer by w-byte integer". The w argument "can either be given as argument or on top of the stack." Therefore, 'ass 4' would pop the 4-byte integer from the stack, but 'ass' would pop the size w from the stack, then pop the w-byte integer. PowerPC ncg wrongly implemented 'ass' as if it was 'ass 4'. Fix it to accept only 'ass 4'.
2016-12-09 22:32:42 +00:00
pat loc ass $1==4 && $2==4 /* Drop 4 bytes from stack */
For "pat ass", move fake stack to real stack before adjusting SP. This fixes code that tried to "addi SP, SP, 4" to drop a value that was in a register, not on the real stack. Add a rule to optimize "asp 4" (which becomes "loc 4" "ass") when the value being dropped is already in a GPR.
2016-09-28 04:13:35 +00:00
with exact GPR
/* nop */
with STACK
gen
addi SP, SP, {CONST, 4}
Fix ass to match the EM spec. The spec says, "ASS w: Adjust the stack pointer by w-byte integer". The w argument "can either be given as argument or on top of the stack." Therefore, 'ass 4' would pop the 4-byte integer from the stack, but 'ass' would pop the size w from the stack, then pop the w-byte integer. PowerPC ncg wrongly implemented 'ass' as if it was 'ass 4'. Fix it to accept only 'ass 4'.
2016-12-09 22:32:42 +00:00
pat ass $1==4 /* Adjust stack by variable amount */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST2 STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
move {SUM_RC, SP, %1.val}, SP
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_HZ STACK
gen
move {SUM_RC, SP, his(%1.val)}, SP
with CONST_ALL-CONST2-CONST_HZ STACK
gen
move {SUM_RC, SP, his(%1.val)}, SP
move {SUM_RC, SP, los(%1.val)}, SP
For "pat ass", move fake stack to real stack before adjusting SP. This fixes code that tried to "addi SP, SP, 4" to drop a value that was in a register, not on the real stack. Add a rule to optimize "asp 4" (which becomes "loc 4" "ass") when the value being dropped is already in a GPR.
2016-09-28 04:13:35 +00:00
with GPR STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
move {SUM_RR, SP, %1}, SP
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat asp /* Adjust stack by constant amount */
leaving
loc $1
Fix ass to match the EM spec. The spec says, "ASS w: Adjust the stack pointer by w-byte integer". The w argument "can either be given as argument or on top of the stack." Therefore, 'ass 4' would pop the 4-byte integer from the stack, but 'ass' would pop the size w from the stack, then pop the w-byte integer. PowerPC ncg wrongly implemented 'ass' as if it was 'ass 4'. Fix it to accept only 'ass 4'.
2016-12-09 22:32:42 +00:00
ass 4
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Floating point support */
/* All very cheap and nasty --- this needs to be properly integrated into
* the code generator. ncg doesn't like having separate FPU registers. */
Check in incomplete Linux PowerPC and M68K work. --HG-- branch : dtrg-experimental-powerpc
2013-05-07 23:48:48 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Single-precision */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zrf $1==INT32 /* Push zero */
leaving
loe ".fs_00000000"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat adf $1==INT32 /* Add single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fadds %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbf $1==INT32 /* Subtract single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fsubs %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat mlf $1==INT32 /* Multiply single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fmuls %a, %2, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dvf $1==INT32 /* Divide single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fdivs %a, %2, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ngf $1==INT32 /* Negate single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fneg %a, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat cmf $1==INT32 /* Compare single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
yields {TRISTATE_FF, %2.1, %1.1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cff $1==INT32 && $2==INT64 /* Convert single to double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG
yields %1.1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cfu $1==INT32 && $2==INT32 /* Convert single to unsigned int */
with STACK
gen
bl {LABEL, ".cfu4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cfi $1==INT32 && $2==INT32 /* Convert single to signed int */
with STACK
gen
bl {LABEL, ".cfi4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cif $1==INT32 && $2==INT32 /* Convert integer to single */
with STACK
gen
bl {LABEL, ".cif4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cuf $1==INT32 && $2==INT32 /* Convert unsigned int to single */
with STACK
gen
bl {LABEL, ".cuf4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat fef $1==INT32 /* Split single */
with STACK
gen
bl {LABEL, ".fef4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Double-precision */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zrf $1==INT64 /* Push zero */
leaving
lde ".fd_00000000"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat adf $1==INT64 /* Add double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fadd %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbf $1==INT64 /* Subtract double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fsub %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat mlf $1==INT64 /* Multiply double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fmul %a, %2, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dvf $1==INT64 /* Divide double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fdiv %a, %2, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ngf $1==INT64 /* Negate double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fneg %a, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat cmf $1==INT64 /* Compare double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
yields {TRISTATE_FF, %2, %1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cff $1==INT64 && $2==INT32 /* Convert double to single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
frsp %a, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cfu $1==INT64 && $2==INT32 /* Convert double to unsigned int */
with STACK
gen
bl {LABEL, ".cfu8"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cfi $1==INT64 && $2==INT32 /* Convert double to signed int */
with STACK
gen
bl {LABEL, ".cfi8"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cif $1==INT32 && $2==INT64 /* Convert integer to double */
with STACK
kills ALL
gen
bl {LABEL, ".cif8"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cuf $1==INT32 && $2==INT64 /* Convert unsigned int to double */
with STACK
gen
bl {LABEL, ".cuf8"}
Rewrite .fif8 to avoid powerpc64 fctid This fixes the SIGILL (illegal instruction) in startrek when firing phasers. The 32-bit processors in my PowerPC Mac and in QEMU don't have fctid, a 64-bit instruction. I got the idea from mach/proto/fp/fif8.c to extract the exponent, clear some bits to get an integer, then subtract the integer from the original value to get the fraction.
2016-10-17 04:39:59 +00:00
pat fef $1==INT64 /* Split exponent, fraction */
Rewrite fef 8 in powerpc assembly. In EM, fef splits a float into exponent and fraction. The old C code, given an infinite float, got stuck in an infinite loop. The new assembly code doesn't loop; it extracts the IEEE exponent.
2016-09-29 19:52:54 +00:00
with GPR3 GPR4
kills FPR0, FPR1, GPR6, GPR7
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Rewrite fef 8 in powerpc assembly. In EM, fef splits a float into exponent and fraction. The old C code, given an infinite float, got stuck in an infinite loop. The new assembly code doesn't loop; it extracts the IEEE exponent.
2016-09-29 19:52:54 +00:00
bl {LABEL, ".fef8"}
yields R4 R3 R5
Rewrite .fif8 to avoid powerpc64 fctid This fixes the SIGILL (illegal instruction) in startrek when firing phasers. The 32-bit processors in my PowerPC Mac and in QEMU don't have fctid, a 64-bit instruction. I got the idea from mach/proto/fp/fif8.c to extract the exponent, clear some bits to get an integer, then subtract the integer from the original value to get the fraction.
2016-10-17 04:39:59 +00:00
pat fif $1==INT64 /* Multiply then split integer, fraction */
with FPR1 FPR2
kills FPR1, FPR2, GPR3, GPR4, GPR5, GPR6
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
bl {LABEL, ".fif8"}
Rewrite .fif8 to avoid powerpc64 fctid This fixes the SIGILL (illegal instruction) in startrek when firing phasers. The 32-bit processors in my PowerPC Mac and in QEMU don't have fctid, a 64-bit instruction. I got the idea from mach/proto/fp/fif8.c to extract the exponent, clear some bits to get an integer, then subtract the integer from the original value to get the fraction.
2016-10-17 04:39:59 +00:00
yields F1 F2
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