Use extended "mr" instead of basic "or" to move registers. Both "mr"
and "or" encode the same machine instruction. With "mr", I can more
easily search the assembly output for register moves.
Fold several stacking rules into a single rule ANY_BHW-REG to STACK.
Remove the EM patterns for loc mlu $2==2 and loc slu. The first
pattern had the wrong size (should be $2==4, not $2==2). Both
patterns were redundant. They rewrote loc mlu as loc mli and loc slu
as loc sli, but this table doesn't have patterns for loc mli or loc
sli, so it is enough to rewrite mlu as mli and slu as sli.
Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with
the rules to use them. These rules emit shorter code. For example,
loading a byte becomes lis, lbz instead of lis, addi, lbz.
While making this, I wrongly set IND_RL_D to size 4. Then ncg made
infinite recursion in codegen() and stackupto(), until it crashed by
stack overflow. I correctly set IND_RL_D to size 8, preventing the
crash.
Remove coercion from LABEL to REG. The coercion never happens because
I have stopped putting LABEL on the stack. Also remove LABEL from set
ANY_BHW. Retain the move from LABEL to REG because pat gto uses it.
Remove li32 instruction, unused after the switch to the hi16, ha16,
lo16 syntax.
Remove COMMENT(...) lines from most moves. In my opinion, they took
too much space, both in the table and in the assembly output. The
stacking rules and coercions keep their COMMENT(...) lines.
In test GPR, don't write to RSCRATCH.
Fold several coercions into a single coercion from ANY_BHW uses REG.
Use REG instead of GPR in stack patterns. REG and GPR act the same,
because every GPR on the stack is a REG, but I want to be clear that I
expect a REG, not r0.
In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later.
Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the
peephole optimizer can optimize it. If $2!=$4, then the EM program is
missing a conversion from size $2 to size $4.
Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These
rules would never get used, unless the EM program is missing a
conversion from size 4 to size 1 or 2.
Use it to generate code like
lis r12,ha16[__II0]
lis r11,ha16[_f]
lfs f1,lo16[_f](r11)
lfs f2,lo16[__II0](r12)
fadds f13,f2,f1
stfs f13,lo16[_f](r11)
Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again
in stfs. Before this change, we needed an extra lis before stfs,
because ncg did not remember that ha16[_f] was in a register.
This example has a gap between ha16[__II0] and lo16[__II0], because
the lo16 is not in the next instruction. This requires my previous
commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis
as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a
coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but
may not allocate any other registers. So I must allocate r12 earlier.
I allocate r12 in pat lae, but this causes a gap.
A 4-byte load from a label yields a token IND_RL_W. This token emits
either lis/lwz or lis/lfs, if we want a general-purpose register or a
floating-point register.
Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands
to instructions. We no longer need to unpack an IND_RC_* token and
repack it as a GPRINDIRECT to use it in an instruction.
Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a
set ANY_BHW for anything that we can store in a regvar.
Push register variables on the stack without using GPRE, by changing
stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN
LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from
mach/arm/ncg/table.)
Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not
a register. We might need to kill the token with "kills MEMORY".
Rename CONST_ALL to CONST_STACK, because it only includes constants on
the stack, and excludes CONST tokens. Instructions still don't allow
CONST_STACK operands, so we still need to repack each CONST_STACK as a
CONST to use it in an instruction.
Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and
LABEL_HO.
The new relocation type RELOLIS handles these instructions:
lis RT, ha16[expr] == addis RT, r0, ha16[expr]
lis RT, hi16[expr] == addis RT, r0, hi16[expr]
RELOLIS stores a 32-bit value in the program text. In this value, the
high bit is a ha16 flag, the next 5 bits are the target register RT,
and the low bits are a signed 26-bit offset. The linker replaces this
value with the lis instruction.
The old RELOPPC relocated a ha16/lo16 or hi16/lo16 pair. The new
RELOLIS relocates only a ha16 or hi16, so it is no longer necessary to
have a matching lo16 in the next instruction. The disadvantage is
that RELOLIS has only a signed 26-bit offset, not a 32-bit offset.
Switch the assembler to use RELOLIS for ha16 or hi16 and RELO2 for
lo16. The li32 instruction still uses the old RELOPPC relocation.
This is not the same as my RELOPPC change from my recent mail to
tack-devel (https://sourceforge.net/p/tack/mailman/message/35651528/).
This commit is on a different branch. Here I am throwing away my
RELOPPC change and instead trying RELOLIS.
We should not include a system header file here, because
mach/proto/as/comm2.y goes through cpp twice. The include can cause
problems like https://github.com/davidgiven/ack/issues/1
Remove this include #<stdbool.h> and leave a comment pointing to the
includes in comm0.h. Change the few instances of bool, false, true,
to int, 0, 1.
Type word_t is for encoding the machine instructions. It only needs
32 bits for PowerPC. It was long (which can have 32 or 64 bits), and
there was a second type quad (which was uint32_t). Switch word_t to
uint32_t and replace quad with word_t.
Also change valu_t and ADDR_T away from long.
They must use OP_RA_RS_RB_C instead of OP_RS_RA_RB_C. The code
generator often sets RS and RA to the same register, so swapping them
causes no change in many programs.
I also rename OP_RS_RA_UI_CC to OP_RA_RS_UI_CC, and OP_RS_RA_C to
OP_RA_RS_C, because they already swap RA and RS.
r0 is a special case and can't be used when adding a register to a
constant. The few remaining users of the scratch register don't do
that. I removed other usages of the scratch register in 7c64dab,
5b5f774, 19f0eb8, f64b7d8.
Also don't delete addis r0, r0, 0. These instructions are special
cases that set r0 to zero. If we delete them, then r0 keeps its old
value.
I caught this bug because osxppc protects the .text segment against
writing. (linuxppc doesn't protect it.) A program tried to set r0 to
the NULL pointer, but top deleted the instruction, so r0 kept an old
return address pointing into .text. Later the program checked that r0
wasn't NULL, tried to write to address r0, and crashed.
The rewritten code rules bring 3 new features:
1. The new rules compare a small constant with a register by
reversing the comparison and using `cmpwi` or `cmplwi`. The old
rules put the constant in a register.
2. The new rules emit shorter code to yield the test results,
without referencing the tables in mach/powerpc/ncg/tge.s.
3. The new rules use the extended `beq` and relatives, not the
basic `bc`, in the assembly output.
I delete the old tristate tokens and the old moves, because they
confused me. Some of the old moves weren't really moves. For
example, `move R3, C0` and then `move C0, R0` did not move r3 to r0.
I rename C0 to CR0.
This fixes the coercion from IND_ALL_D to FREG. The coercion had
never happened, because IND_ALL_D had 8 bytes but FREG had 4 bytes.
Instead, ncg always stacked the IND_ALL_D and unstacked a FREG. The
stacking rule uses f0, so the code did load f0 with the indirect
value, push f0 to stack, load f1 to stack, move stack pointer. Now
that FREG has 8 bytes, ncg does the coercion, and the code just loads
f1 with the indirect value.
Always use 'kills ALL' when reaching a label, because our registers
and tokens have the wrong values if the program jumps to this label
from somewhere else.
When falling through a label, if the top element is in r3, then
require that the rest of the stack is in the real STACK, not in
registers or tokens.
I'm doing this to be certain that the missing constraints are not
causing bugs. I did not find any such bug, perhaps because the labels
are usually near other instructions (like conditional branches and
function calls) that stack or kill tokens.
This is for fef 8 and fif 8. I changed .fef8 so it no longer kills
r7, but I don't want to update the list. We already use "kills ALL"
for most other calls to libem.
The new features are the hi16/lo16 and ha16/lo16 syntax for
relocations, and the extended mnemonics like "blr".
Use ha16/lo16 to load some double floats with 2 instructions (lis/lfd)
instead of 3 (lis/ori/lfd).
Use the extended names for branches, comparisons, and bit rotations,
so I can more easily read the code. The new names often encode the
same machine instructions as the old names, except in a few places
where I changed the instructions.
Stop using andi. when we don't need to set cr0. In inn.s, I change
andi. to extrwi to extract the same bits. In los.s and sts.s, I
change "andi. r3, r3, ~3" to "clrrwi r3, r3, 2". This avoids setting
cr0 and also stops clearing the high 16 bits of r3.
In csa.s, los.s, sts.s, I change some comparisons and right shifts
from signed to unsigned (cmplw, cmplwi, srwi), because the sizes are
unsigned. In inn.s, the right shift can be signed (sraw) or unsigned
(srw), but I use srw because we don't need the carry bit.
In fef8.s, I save an instruction by using rlwinm instead of addis/andc
to rlwinm to clear a field. The code no longer kills r7. In both
fef8.s and fif8.s, I remove the list of killed registers.
Also remove some whitespace from ends of lines.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
possible values. Add the PowerPC ncg and mcg backend support to let the test
actually run, including modifying a bunch of PowrePC libem functions so that
they can be called from both ncg and mcg.
assembler directives, ha16() and has16(), for the upper half; has16() applies
the sign adjustment. .powerpcfixup is now gone, as we generate the relocation
in ha*() instead. Add special logic to the linker for undoing and redoing the
sign adjustment when reading/writing fixups. Tests still pass.
This provides and, ior, xor, com, zer, set, cms when defined($1) and
ior, set when !defined($1). I don't provide the other operations
!defined($1) because our Modula-2 compiler hasn't used them.
I wrote a Modula-2 example in
https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788
Put a dummy comment in mach/powerpc/libem/build.lua so git checkout
will touch that file. Without the touch, the build system doesn't see
the new *.s files.
We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes
other than 4. Add clause $1==4.
We only implement inn when defined($1).
The rule for aar needs 'kills ALL' because it kills many registers,
like other rules that call libem.
This allows 'move {CONST, $1}, R3' with a small enough $1 to emit one
instruction (addi) instead of two instructions (addis, ori). The
CONST token confusingly isn't in the CONST_ALL set.
The spec says, "ASS w: Adjust the stack pointer by w-byte integer".
The w argument "can either be given as argument or on top of the
stack." Therefore, 'ass 4' would pop the 4-byte integer from the
stack, but 'ass' would pop the size w from the stack, then pop the
w-byte integer.
PowerPC ncg wrongly implemented 'ass' as if it was 'ass 4'. Fix it to
accept only 'ass 4'.
These instructions would load or store the EM heap pointer. They
don't work. Programs must use brk() or sbrk() in libsys.
The last file to use 'lor 2' and 'str 2' was lang/pc/libpc/sav.e in
the Pascal library. Commit c084f9f deleted the file, so we no longer
need rules 'lor 2' or 'str 2' to build the ACK.
PowerPC has a few hundred special-purpose registers. The assembler
had only accepted the names "xer", "lr", "ctr". Most programs use
only those three SPRs. If I add more names, they would almost never
get used, and they might conflict with labels.
I want to use "mfspr r3, 0x3f0" and "mtspr 0x3f0, r3" in
plat/qemu/boot.s to access register hid0 from supervisor mode.
corresponding invocation in the ncg table so the same helpers can be used for
both mcg and ncg. Add a new IR opcode, FARJUMP, which jumps to a helper
function but saves volatile registers.
