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riscv: Add sar, shr insn

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fixes 92_enum_bitfield.
This commit is contained in:
Michael Matz 2019-07-15 19:34:08 +02:00
parent f64d460d29
commit 215bc1aab4
1 changed files with 6 additions and 2 deletions
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8
riscv64-gen.c
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@ -621,8 +621,6 @@ static void gen_opil(int op, int ll)
d = ireg(d); d = ireg(d);
switch (op) { switch (op) {
case '%': case '%':
case TOK_SAR:
case TOK_SHR:
case TOK_PDIV: case TOK_PDIV:
default: default:
tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL)); tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL));
@ -633,6 +631,12 @@ static void gen_opil(int op, int ll)
case '-': case '-':
o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); //sub d, a, b o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); //sub d, a, b
break; break;
case TOK_SAR:
o(0x33 | (d << 7) | (a << 15) | (b << 20) | (5 << 12) | (1 << 30)); //sra d, a, b
break;
case TOK_SHR:
o(0x33 | (d << 7) | (a << 15) | (b << 20) | (5 << 12)); //srl d, a, b
break;
case TOK_SHL: case TOK_SHL:
o(0x33 | (d << 7) | (a << 15) | (b << 20) | (1 << 12)); //sll d, a, b o(0x33 | (d << 7) | (a << 15) | (b << 20) | (1 << 12)); //sll d, a, b
break; break;