65oo2/doc/isa.org

97 lines
4.2 KiB
Org Mode

#+title: 65∞2 Instruction Set Architecture
#+author: d0p1
** Registers
- PC :: Program counter (32bit)
- A :: Accumulator (32bit)
- D :: Direct register (32bit)
- X :: X index register (32bit)
- Y :: Y index register (32bit)
- SR :: status register (8bit)
- SP :: stack pointer (32bit)
Status register flags
#+begin_src
31 0
+------ .... ----+-+-+-+-+-+-+-+-+
| |N|V| |B|D|I|Z|C|
+------ .... ----+-+-+-+-+-+-+-+-+
#+end_src
- N :: Negative
The negative flag (N) indicates the presence of a set sign bit in bit-position 31.
- V :: Overflow
The overflow flag (V) indicates overflow with signed binary arithmetics.
- B :: Break
- D :: Decimal
- I :: Interrupt
- Z :: Zero
The zero flag (Z) indicates a value of all zero bits.
- C :: Carry
** Addressing Modes
*** Implied Addressing
*** Remative Addressing
*** Immediate Addressing
A size and a literal operand is given immediately after the instruction.
#+begin_src asm
LDA.B #7
LDA.W #300
LDA.L #$DEADBEEF
LDA.SB #-5 ! sign extended
LDA.SW #-5367 ! sign extended
#+end_src
*** Absolute Addressing
** Opcodes
| | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
|----|----------|-----------|-------|----|----|----|----|----|----------|-----------|----------|----|-----------|-----------|-----------|----|
| 0- | BRK impl | ORA X,ind | | | | | | | PHP impl | ORA # | ASL A | | | ORA abs | ASL abs | |
| 1- | BPL rel | ORA ind,Y | | | | | | | CLC impl | ORA abs,Y | | | | ORA abs,X | ASL abs,X | |
| 2- | JSR abs | AND X,ind | | | | | | | PLP impl | AND # | ROL A | | BIT abs | AND abs | ROL abs | |
| 3- | BMI rel | AND ind,Y | | | | | | | SEC impl | AND abs,Y | | | | AND abs,X | ROL abs,X | |
| 4- | RTI impl | EOR X,ind | | | | | | | PHA impl | EOR # | LSR A | | JMP abs | EOR abs | LSR abs | |
| 5- | BVC rel | EOR ind,Y | | | | | | | CLI impl | EOR abs,Y | | | | EOR abs,X | LSR abs,X | |
| 6- | RTS impl | ADC X,ind | PER? | | | | | | PLA impl | ADC # | ROR A | | JMP ind | ADC abs | ROR abs | |
| 7- | BVS rel | ADC ind,Y | | | | | | | SEI impl | ADC abs,Y | | | | ADC abs,X | ROR abs,X | |
| 8- | | STA X,ind | | | | | | | DEY impl | | TXA impl | | STY abs | STA abs | STX abs | |
| 9- | BCC rel | STA ind,Y | | | | | | | TYA impl | STA abs,Y | TXS impl | | | STA abs,X | | |
| A- | LDY # | LDA X,ind | LDX # | | | | | | TAY impl | LDA # | TAX impl | | LDY abs | LDA abs | LDX abs | |
| B- | BCS rel | LDA ind,Y | | | | | | | CLV impl | LDA abs,Y | TSX impl | | LDY abs,X | LDA abs,X | LDX abs,Y | |
| C- | CPY # | CMP X,ind | | | | | | | INY impl | CMP # | DEX impl | | CPY abs | CMP abs | DEC abs | |
| D- | BNE rel | CMP ind,Y | | | | | | | CLD impl | CMP abs,Y | | | | CMP abs,X | DEC abs,X | |
| E- | CPX # | SBC X,ind | | | | | | | INX impl | SBC # | NOP impl | | CPX abs | SBC abs | INC abs | |
| F- | BEQ rel | SBC ind,Y | | | | | | | SED impl | SBC abs,Y | | | | SBC abs,X | INC abs,X | |
** Instruction encoding
| 0-7 |
|--------|
| opcode |
| 0-7 | 8-21 |
|--------|---------------|
| opcode | relative addr |
| 0-7 | 8-15 | 16-X |
|--------|------|-------|
| opcode | attr | value |
** Instructions Listing
- ADC :: add with carry
- AND :: and (with accumulator)
- ASL :: arithmetic shift left
- BCC :: branch on carry clear
- BCS :: branch on carry set
- BEQ :: branch on equa (zero set)