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Author SHA1 Message Date
David Given
f67c98e239 Distributions are a pain --- let's not bother any more. Instead, we just tag 
the repository and download a complete snapshot, old and ancient stuff and all.
 2016-09-02 23:00:38 +02:00
David Given
612e38f1c6 Remove the old make-based build system, plus some big chunks of horribly 
obsolete protomake build system.
 2016-09-02 22:17:51 +02:00
David Given
204f932ed2 Raspberry Pi backend now builds. 2016-08-20 12:40:13 +02:00
David Given
62cc636f10 Merge. 
--HG--
branch : dtrg-videocore
 2015-03-23 00:15:42 +01:00
David Given
e36d739fa4 Add (largely untested) float/int conversion. 
--HG--
branch : dtrg-videocore
 2013-07-01 13:05:36 +01:00
David Given
8b6951dac0 Fix incorrect offset encoding in lea (sp) instructions. 
--HG--
branch : dtrg-videocore
 2013-06-29 00:35:07 +01:00
David Given
edb174da8d Fix incorrect encoding of 'push lr' and 'pop pc'. 
--HG--
branch : dtrg-videocore
 2013-06-29 00:32:39 +01:00
David Given
29af6f1adb ISA change: clz has been renamed to log2. 
--HG--
branch : dtrg-videocore
 2013-06-27 11:25:50 +01:00
David Given
2b3f95de0b Fix jump range checking in the addcmpb family of instructions. 
--HG--
branch : dtrg-videocore
 2013-06-26 23:32:54 +01:00
David Given
d94c1c8150 Updated distr files. 
--HG--
branch : dtrg-videocore
rename : mach/i80/.distr => mach/vc4/.distr
rename : plat/cpm/.distr => plat/rpi/.distr
 2013-06-21 23:38:21 +01:00
David Given
bbd4b46850 Fix stack corruption when adjusting SP. Be a bit more rigorous about clearing the pseudostack on branch/labels. 
--HG--
branch : dtrg-videocore
 2013-06-07 21:25:38 +01:00
David Given
3e0123ca03 Fix treatment of out-of-range values in switch csa. 
--HG--
branch : dtrg-videocore
 2013-06-05 23:57:23 +01:00
David Given
86c6fa2f1e Implement NOT... 
--HG--
branch : dtrg-videocore
 2013-05-30 23:50:19 +01:00
David Given
1f36370d87 Implement nop (the C compiler sometimes generates this!). 
--HG--
branch : dtrg-videocore
 2013-05-26 22:54:53 +01:00
David Given
ef25c53c9c Fix bug in ine/dee. 
--HG--
branch : dtrg-videocore
 2013-05-26 18:59:19 +01:00
David Given
366cd10194 Remainders are calculated correctly. printf now works. 
--HG--
branch : dtrg-videocore
 2013-05-26 13:13:58 +01:00
David Given
510888e6d5 .csb now works. 
--HG--
branch : dtrg-videocore
rename : mach/vc4/libem/csa.s => mach/vc4/libem/csb.s
 2013-05-26 13:06:25 +01:00
David Given
6284512b37 Fix erroneous section check (symbols may not have a defined section in pass 1). 
--HG--
branch : dtrg-videocore
 2013-05-26 00:35:15 +01:00
David Given
308d41e083 Added triple-quad load and store (used by the signal stuff). 
--HG--
branch : dtrg-videocore
 2013-05-26 00:22:08 +01:00
David Given
8c21a2ef9b Stop fighting the terrible code and remove the regvar support --- it didn't help much and was a pain. 
--HG--
branch : dtrg-videocore
 2013-05-25 23:58:35 +01:00
David Given
3b07fee160 Major bugfix where instructions weren't being shrunk correctly. (Turns out there's built-in support for doing this, which I hadn't found.) 
--HG--
branch : dtrg-videocore
 2013-05-25 23:26:10 +01:00
David Given
b6680a48cc Disable register variables. The code is a bit worse, but having two stackable registers makes things much easier to understand. 
--HG--
branch : dtrg-videocore
 2013-05-25 13:31:58 +01:00
David Given
d7efb0a32c Implement .csa. 
--HG--
branch : dtrg-videocore
rename : mach/vc4/libem/dummy.s => mach/vc4/libem/csa.s
 2013-05-25 13:31:27 +01:00
David Given
2ee79ab0b2 Encode comparing branch correctly. 
--HG--
branch : dtrg-videocore
 2013-05-25 13:31:01 +01:00
David Given
472f778342 Don't write out constant data as big-endian! Some other cleanups. 
--HG--
branch : dtrg-videocore
 2013-05-25 00:33:38 +01:00
David Given
98a51732ab Various codegen tweaks. 
--HG--
branch : dtrg-videocore
 2013-05-24 17:04:29 +01:00
David Given
2c7ee27206 Double-quads can be loaded and stored (more) correctly. 
--HG--
branch : dtrg-videocore
 2013-05-22 23:55:23 +01:00
David Given
6cbe6e1c4e Better treatment of sign extension. 
--HG--
branch : dtrg-videocore
 2013-05-22 23:12:48 +01:00
David Given
7537c85e0a Generate adds instructions when a shift-and-add is seen (useful for array indexing). 
--HG--
branch : dtrg-videocore
 2013-05-22 21:37:48 +01:00
David Given
cdce394b6c Generate ld rd, (rs) instructions properly. 
--HG--
branch : dtrg-videocore
 2013-05-22 11:02:46 +01:00
David Given
9e556d8b7b Optimise direct access to globals, and incrementing and decrementing locals. 
--HG--
branch : dtrg-videocore
 2013-05-22 10:55:13 +01:00
David Given
08c4334224 Typo fixes. 
--HG--
branch : dtrg-videocore
 2013-05-22 00:44:04 +01:00
David Given
f904465e9c Fix signedness problem that was showing up on ARM. 
--HG--
branch : dtrg-videocore
 2013-05-22 00:16:16 +01:00
David Given
5e9102955c Reworked VC4 relocations and some of the instruction encoding to be actually correct. Now generating what could be real code! 
--HG--
branch : dtrg-videocore
 2013-05-21 23:17:30 +01:00
David Given
1312fe298b Now compiles (incorrectly) the entire libc, libpc, libm2 and libbasic! 
--HG--
branch : dtrg-videocore
 2013-05-21 20:05:26 +01:00
David Given
877e06ed89 Lots more opcodes including float support. Define float and double to be the 
same thing (as the VC4 seems not to have double-precision float support).

--HG--
branch : dtrg-videocore
 2013-05-21 18:16:30 +01:00
David Given
6cdea73e84 Add a lot more opcodes. 
--HG--
branch : dtrg-videocore
 2013-05-20 23:27:45 +01:00
David Given
d6565f4d5b Fix typo. 
--HG--
branch : dtrg-videocore
 2013-05-20 23:27:31 +01:00
David Given
970f2bae62 Major revamp to simplify and use 2op instructions. Better code. Now looks like it may work one day. 
--HG--
branch : dtrg-videocore
 2013-05-20 22:35:12 +01:00
David Given
5082b2a5d7 Add lea instruction. Fix dependency issues. 
--HG--
branch : dtrg-videocore
 2013-05-20 19:56:33 +01:00
David Given
11890026db Push/pop are the right way round. Don't corrup short-form ALU instructions. Correct encoding of push/pop register ranges. 
--HG--
branch : dtrg-videocore
 2013-05-19 23:34:42 +01:00
David Given
76ba0bf6b3 First steps towards a code generator. 
--HG--
branch : dtrg-videocore
 2013-05-19 23:33:42 +01:00
David Given
80f85001fa Correctly emit constants in some ALU instructions. 
--HG--
branch : dtrg-videocore
 2013-05-19 23:19:10 +01:00
David Given
4f15423d63 Add compare-and-branch instructions. 
--HG--
branch : dtrg-videocore
 2013-05-19 18:40:19 +01:00
David Given
80afe75c9b Added memory operations that work on fixed up addresses. 
--HG--
branch : dtrg-videocore
 2013-05-19 13:03:53 +01:00
David Given
febe8ca937 Add register offset and postincrement memory operations. 
--HG--
branch : dtrg-videocore
 2013-05-19 12:39:35 +01:00
David Given
fc2833d456 Add most vanilla memory load/store instructions. 
--HG--
branch : dtrg-videocore
 2013-05-19 00:56:56 +01:00
David Given
26877d3c4f Add a whole bunch of VC4 opcodes. 
--HG--
branch : dtrg-videocore
 2013-05-17 23:30:49 +01:00
David Given
32ebc502c8 Skeleton of VideoCore IV support for the Raspberry Pi. 
--HG--
branch : dtrg-videocore
rename : mach/powerpc/as/.distr => mach/vc4/as/.distr
rename : mach/powerpc/as/mach0.c => mach/vc4/as/mach0.c
rename : mach/powerpc/as/mach1.c => mach/vc4/as/mach1.c
rename : mach/powerpc/as/mach2.c => mach/vc4/as/mach2.c
rename : mach/powerpc/as/mach3.c => mach/vc4/as/mach3.c
rename : mach/powerpc/as/mach4.c => mach/vc4/as/mach4.c
rename : mach/powerpc/as/mach5.c => mach/vc4/as/mach5.c
rename : mach/i86/build.mk => mach/vc4/build.mk
rename : mach/powerpc/libem/powerpc.h => mach/vc4/libem/videocore.h
rename : mach/i86/libend/.distr => mach/vc4/libend/.distr
rename : mach/i86/libend/edata.s => mach/vc4/libend/edata.s
rename : mach/i86/libend/em_end.s => mach/vc4/libend/em_end.s
rename : mach/i86/libend/end.s => mach/vc4/libend/end.s
rename : mach/i86/libend/etext.s => mach/vc4/libend/etext.s
rename : mach/powerpc/ncg/.distr => mach/vc4/ncg/.distr
rename : mach/powerpc/ncg/mach.c => mach/vc4/ncg/mach.c
rename : mach/powerpc/ncg/mach.h => mach/vc4/ncg/mach.h
rename : mach/powerpc/ncg/table => mach/vc4/ncg/table
rename : plat/pc86/descr => plat/rpi/descr
 2013-05-17 00:03:38 +01:00