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Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
EM_WSIZE = 4
EM_PSIZE = 4
EM_BSIZE = 8 /* two words saved in call frame */
INT8 = 1 /* Size of values */
INT16 = 2
INT32 = 4
INT64 = 8
FP_OFFSET = 0 /* Offset of saved FP relative to our FP */
PC_OFFSET = 4 /* Offset of saved PC relative to our FP */
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
SL_OFFSET = 8 /* Offset of static link */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Turn off comments again. I turned them on by accident in c416889.
2017-01-30 20:45:46 +00:00
#define COMMENT(n) /* comment {LABEL, n} */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
#define nicesize(x) ((x)==INT8 || (x)==INT16 || (x)==INT32 || (x)==INT64)
#define smalls(n) sfit(n, 16)
#define smallu(n) ufit(n, 16)
In powerpc table, fix macros los() and his(). Change the operator in his() from a - minus to a + plus. When los(n) becomes negative, then his(n) needs to add 0x10000, not subtract it. Also change los(n) to do the sign extension, because smalls(los(n)) should be true, not false. Also change hi(n) and lo(n) to wrap n in parentheses, as (n), because these are macros and n might still contain operators.
2016-10-15 03:59:26 +00:00
#define lo(n) ((n) & 0xFFFF)
#define hi(n) (((n)>>16) & 0xFFFF)
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Use these for instructions that treat the low half as signed --- his()
* includes a modifier to produce the correct value when the low half gets
* sign extended. Er, do make sure you load the low half second. */
In powerpc table, fix macros los() and his(). Change the operator in his() from a - minus to a + plus. When los(n) becomes negative, then his(n) needs to add 0x10000, not subtract it. Also change los(n) to do the sign extension, because smalls(los(n)) should be true, not false. Also change hi(n) and lo(n) to wrap n in parentheses, as (n), because these are macros and n might still contain operators.
2016-10-15 03:59:26 +00:00
#define los(n) (lo(n) | (((0-(lo(n)>>15)) & ~0xFFFF)))
#define his(n) ((hi(n) + (lo(n)>>15)) & 0xFFFF)
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
PROPERTIES
GPR /* any GPR */
REG /* any allocatable GPR */
Add missing size declarations for 8-byte registers. This fixes the coercion from IND_ALL_D to FREG. The coercion had never happened, because IND_ALL_D had 8 bytes but FREG had 4 bytes. Instead, ncg always stacked the IND_ALL_D and unstacked a FREG. The stacking rule uses f0, so the code did load f0 with the indirect value, push f0 to stack, load f1 to stack, move stack pointer. Now that FREG has 8 bytes, ncg does the coercion, and the code just loads f1 with the indirect value.
2017-01-25 16:24:23 +00:00
FPR(8) /* any FPR */
FREG(8) /* any allocatable FPR */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
FSREG /* any allocatable single-precision FPR */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SPR /* any SPR */
CR /* any CR */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
REGISTERS
/* Reverse order to encourage ncg to allocate them from r31 down */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
r31, r30, r29, r28, r27, r26,
r25, r24, r23, r22, r21, r20,
r19, r18, r17, r16, r15, r14,
r13 : GPR, REG regvar.
r12, r11, r10, r9, r8, r7,
r6, r5, r4, r3 : GPR, REG.
fp, sp, r0 : GPR.
Check in incomplete Linux PowerPC and M68K work. --HG-- branch : dtrg-experimental-powerpc
2013-05-07 23:48:48 +00:00
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
/* f31 to f14 are reserved for regvar. */
f13, f12, f11, f10, f9, f8
f7, f6, f5, f4, f3, f2, f1 : FPR, FREG.
f0 : FPR.
fs13("f13")=f13, fs12("f12")=f12,
fs11("f11")=f11, fs10("f10")=f10,
fs9("f9")=f9, fs8("f8")=f8,
fs7("f7")=f7, fs6("f6")=f6,
fs5("f5")=f5, fs4("f4")=f4,
fs3("f3")=f3, fs2("f2")=f2,
fs1("f1")=f1 : FSREG.
lr, ctr : SPR.
cr0 : CR.
#define RSCRATCH r0
#define FSCRATCH f0
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
TOKENS
/* Primitives */
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
CONST = { INT val; } 4 val.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
LABEL = { ADDR adr; } 4 adr.
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
LABEL_HI = { ADDR adr; } 4 "hi16[" adr "]".
LABEL_HA = { ADDR adr; } 4 "ha16[" adr "]".
LABEL_LO = { ADDR adr; } 4 "lo16[" adr "]".
LOCAL = { INT off; } 4 ">>> BUG IN LOCAL".
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Allows us to use regvar() to refer to registers */
GPRE = { GPR reg; } 4 reg.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
/* Constants on the stack */
CONST_N8000 = { INT val; } 4.
CONST_N7FFF_N0001 = { INT val; } 4.
CONST_0000_7FFF = { INT val; } 4.
CONST_8000 = { INT val; } 4.
CONST_8001_FFFF = { INT val; } 4.
CONST_HZ = { INT val; } 4.
CONST_HL = { INT val; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Expression partial results */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
SUM_RIS = { GPR reg; INT offhi; } 4. /* reg + (offhi << 16) */
SUM_RC = { GPR reg; INT off; } 4. /* reg + off */
SUM_RL = { GPR reg; ADDR adr; } 4. /* reg + lo16[adr] */
SUM_RR = { GPR reg1; GPR reg2; } 4. /* reg1 + reg2 */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SEX_B = { GPR reg; } 4.
SEX_H = { GPR reg; } 4.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
IND_RC_B = { GPR reg; INT off; } 4 off "(" reg ")".
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
IND_RL_B = { GPR reg; ADDR adr; } 4 "lo16[" adr "](" reg ")".
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
IND_RR_B = { GPR reg1; GPR reg2; } 4.
IND_RC_H = { GPR reg; INT off; } 4 off "(" reg ")".
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
IND_RL_H = { GPR reg; ADDR adr; } 4 "lo16[" adr "](" reg ")".
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
IND_RR_H = { GPR reg1; GPR reg2; } 4.
IND_RC_H_S = { GPR reg; INT off; } 4 off "(" reg ")".
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
IND_RL_H_S = { GPR reg; ADDR adr; } 4 "lo16[" adr "](" reg ")".
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
IND_RR_H_S = { GPR reg1; GPR reg2; } 4.
IND_RC_W = { GPR reg; INT off; } 4 off "(" reg ")".
IND_RL_W = { GPR reg; ADDR adr; } 4 "lo16[" adr "](" reg ")".
IND_RR_W = { GPR reg1; GPR reg2; } 4.
IND_RC_D = { GPR reg; INT off; } 8 off "(" reg ")".
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
IND_RL_D = { GPR reg; ADDR adr; } 8 "lo16[" adr "](" reg ")".
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
IND_RR_D = { GPR reg1; GPR reg2; } 8.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
NOT_R = { GPR reg; } 4.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
AND_RR = { GPR reg1; GPR reg2; } 4.
OR_RR = { GPR reg1; GPR reg2; } 4.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
OR_RIS = { GPR reg; INT valhi; } 4.
OR_RC = { GPR reg; INT val; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
XOR_RR = { GPR reg1; GPR reg2; } 4.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
XOR_RIS = { GPR reg; INT valhi; } 4.
XOR_RC = { GPR reg; INT val; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
COND_RC = { GPR reg; INT val; } 4.
COND_RR = { GPR reg1; GPR reg2; } 4.
CONDL_RC = { GPR reg; INT val; } 4.
CONDL_RR = { GPR reg1; GPR reg2; } 4.
COND_FS = { FSREG reg1; FSREG reg2; } 4.
COND_FD = { FREG reg1; FREG reg2; } 4.
XEQ = { GPR reg; } 4.
XNE = { GPR reg; } 4.
XGT = { GPR reg; } 4.
XGE = { GPR reg; } 4.
XLT = { GPR reg; } 4.
XLE = { GPR reg; } 4.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SETS
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
/* signed 16-bit integer */
CONST2 = CONST_N8000 + CONST_N7FFF_N0001 + CONST_0000_7FFF.
/* integer that, when negated, fits signed 16-bit */
CONST2_WHEN_NEG = CONST_N7FFF_N0001 + CONST_0000_7FFF + CONST_8000.
/* unsigned 16-bit integer */
UCONST2 = CONST_0000_7FFF + CONST_8000 + CONST_8001_FFFF.
/* any constant on stack */
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
CONST_STACK = CONST_N8000 + CONST_N7FFF_N0001 + CONST_0000_7FFF +
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
CONST_8000 + CONST_8001_FFFF + CONST_HZ + CONST_HL.
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
SUM_ALL = SUM_RC + SUM_RL + SUM_RR.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
SEX_ALL = SEX_B + SEX_H.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
LOGICAL_ALL = NOT_R + AND_RR + OR_RR + OR_RC + XOR_RR +
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
XOR_RC.
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
IND_ALL_B = IND_RC_B + IND_RL_B + IND_RR_B.
IND_ALL_H = IND_RC_H + IND_RL_H + IND_RR_H +
IND_RC_H_S + IND_RL_H_S + IND_RR_H_S.
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
IND_ALL_W = IND_RC_W + IND_RL_W + IND_RR_W.
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
IND_ALL_D = IND_RC_D + IND_RL_D + IND_RR_D.
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
IND_ALL_BHW = IND_ALL_B + IND_ALL_H + IND_ALL_W.
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
/* anything killed by sti (store indirect) */
MEMORY = IND_ALL_BHW + IND_ALL_D.
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
/* any stack token that we can easily move to GPR */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
ANY_BHW = REG + CONST_STACK + SEX_ALL +
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
SUM_ALL + IND_ALL_BHW + LOGICAL_ALL.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
INSTRUCTIONS
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
/* We give time as cycles of total latency from Freescale
* Semiconductor, MPC7450 RISC Microprocessor Family Reference
* Manual, Rev. 5, section 6.6.
*
* We have only 4-byte alignment for doubles; 8-byte alignment is
* optimal. We guess the misalignment penalty by adding 1 cycle to
* the cost of loading or storing a double:
* lfd lfdu lfdx: 4 -> 5
* stfd stfdu stfdx: 3 -> 4
*/
cost(4, 1) /* space, time */
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
add GPR:wo, GPR:ro, GPR:ro.
addX "add." GPR:wo, GPR:ro, GPR:ro.
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
addi GPR:wo, GPR:ro, CONST+LABEL_LO:ro.
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
li GPR:wo, CONST:ro.
addis GPR:wo, GPR:ro, CONST+LABEL_HI+LABEL_HA:ro.
lis GPR:wo, CONST+LABEL_HI+LABEL_HA:ro.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
and GPR:wo, GPR:ro, GPR:ro.
andc GPR:wo, GPR:ro, GPR:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
andiX "andi." GPR:wo:cc, GPR:ro, CONST:ro.
andisX "andis." GPR:wo:cc, GPR:ro, CONST:ro.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
b LABEL:ro.
bc CONST:ro, CONST:ro, LABEL:ro.
Implement blm and bls using an inline loop. This replaces a call to memmove() in libc. That was working for me, but it can fail because EM programs don't always link to libc. blm and bls only need to copy aligned words. They don't need to copy bytes, and they don't need to copy between overlapping buffers, as memmove() does. So the new loop is simpler than memmove().
2017-02-12 00:30:12 +00:00
bdnz LABEL:ro.
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
beq LABEL:ro.
bne LABEL:ro.
bgt LABEL:ro.
bge LABEL:ro.
blt LABEL:ro.
ble LABEL:ro.
bxx LABEL:ro. /* dummy */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
bcctr CONST:ro, CONST:ro, CONST:ro.
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
bctr.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
bcctrl CONST:ro, CONST:ro, CONST:ro.
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
bctrl.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
bclr CONST:ro, CONST:ro, CONST:ro.
bl LABEL:ro.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
cmp CR:ro, CONST:ro, GPR:ro, GPR:ro kills :cc.
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
cmpw GPR:ro, GPR:ro kills :cc.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
cmpi CR:ro, CONST:ro, GPR:ro, CONST:ro kills :cc.
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
cmpwi GPR:ro, CONST:ro kills :cc.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
cmpl CR:ro, CONST:ro, GPR:ro, GPR:ro kills :cc.
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
cmplw GPR:ro, GPR:ro kills :cc.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
cmpli CR:ro, CONST:ro, GPR:ro, CONST:ro kills :cc.
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
cmplwi GPR:ro, CONST:ro kills :cc.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
divw GPR:wo, GPR:ro, GPR:ro cost(4, 23).
divwu GPR:wo, GPR:ro, GPR:ro cost(4, 23).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
eqv GPR:wo, GPR:ro, GPR:ro.
extsb GPR:wo, GPR:ro.
extsh GPR:wo, GPR:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
fadd FREG:wo, FREG:ro, FREG:ro cost(4, 5).
fadds FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5).
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
fcmpo CR:wo, FREG:ro, FREG:ro cost(4, 5).
fcmpo CR:wo, FSREG:ro, FSREG:ro cost(4, 5).
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
fctiwz FREG:wo, FREG:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
fdiv FREG:wo, FREG:ro, FREG:ro cost(4, 35).
fdivs FSREG:wo, FSREG:ro, FSREG:ro cost(4, 21).
fmr FPR:wo, FPR:ro cost(4, 5).
fmr FSREG:wo, FSREG:ro cost(4, 5).
fmul FREG:wo, FREG:ro, FREG:ro cost(4, 5).
fmuls FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5).
fneg FREG:wo, FREG:ro cost(4, 5).
fneg FSREG:wo, FSREG:ro cost(4, 5).
frsp FSREG:wo, FREG:ro cost(4, 5).
fsub FREG:wo, FREG:ro, FREG:ro cost(4, 5).
fsubs FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5).
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
lbz GPR:wo, IND_RC_B+IND_RL_B:ro cost(4, 3).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
lbzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
lfd FPR:wo, IND_RC_D+IND_RL_D:ro cost(4, 5).
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
lfdu FPR:wo, IND_RC_D:ro cost(4, 5).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
lfdx FPR:wo, GPR:ro, GPR:ro cost(4, 5).
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
lfs FSREG:wo, IND_RC_W+IND_RL_W:ro cost(4, 4).
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
lfsu FSREG:wo, IND_RC_W:rw cost(4, 4).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
lfsx FSREG:wo, GPR:ro, GPR:ro cost(4, 4).
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
lha GPR:wo, IND_RC_H_S+IND_RL_H_S:ro cost(4, 3).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
lhax GPR:wo, GPR:ro, GPR:ro cost(4, 3).
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
lhz GPR:wo, IND_RC_H+IND_RL_H:ro cost(4, 3).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
lhzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
lwzu GPR:wo, IND_RC_W:ro cost(4, 3).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
lwzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
lwz GPR:wo, IND_RC_W+IND_RL_W:ro cost(4, 3).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
nand GPR:wo, GPR:ro, GPR:ro.
neg GPR:wo, GPR:ro.
nor GPR:wo, GPR:ro, GPR:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
mfcr GPR:wo cost(4,2).
mullw GPR:wo, GPR:ro, GPR:ro cost(4, 4).
mfspr GPR:wo, SPR:ro cost(4, 3).
mtspr SPR:wo, GPR:ro cost(4, 2).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
or GPR:wo, GPR:ro, GPR:ro.
Use "mr" and make a few other tweaks in PowerPC ncg table. Use extended "mr" instead of basic "or" to move registers. Both "mr" and "or" encode the same machine instruction. With "mr", I can more easily search the assembly output for register moves. Fold several stacking rules into a single rule ANY_BHW-REG to STACK. Remove the EM patterns for loc mlu $2==2 and loc slu. The first pattern had the wrong size (should be $2==4, not $2==2). Both patterns were redundant. They rewrote loc mlu as loc mli and loc slu as loc sli, but this table doesn't have patterns for loc mli or loc sli, so it is enough to rewrite mlu as mli and slu as sli.
2017-02-10 16:45:50 +00:00
mr GPR:wo, GPR:ro.
orX "or." GPR:wo:cc, GPR:ro, GPR:ro.
orX_readonly "or." GPR:ro:cc, GPR:ro, GPR:ro.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
orc GPR:wo, GPR:ro, GPR:ro.
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
ori GPR:wo, GPR:ro, CONST+LABEL_LO:ro.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
oris GPR:wo, GPR:ro, CONST:ro.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
rlwinm GPR:wo, GPR:ro, CONST:ro, CONST:ro, CONST:ro.
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
extlwi GPR:wo, GPR:ro, CONST:ro, CONST:ro.
extrwi GPR:wo, GPR:ro, CONST:ro, CONST:ro.
Implement blm and bls using an inline loop. This replaces a call to memmove() in libc. That was working for me, but it can fail because EM programs don't always link to libc. blm and bls only need to copy aligned words. They don't need to copy bytes, and they don't need to copy between overlapping buffers, as memmove() does. So the new loop is simpler than memmove().
2017-02-12 00:30:12 +00:00
srwi GPR:wo, GPR:ro, CONST:ro.
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
slw GPR:wo, GPR:ro, GPR:ro.
subf GPR:wo, GPR:ro, GPR:ro.
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
sraw GPR:wo, GPR:ro, GPR:ro cost(4, 2).
srawi GPR:wo, GPR:ro, CONST:ro cost(4, 2).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
srw GPR:wo, GPR:ro, GPR:ro.
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
stb GPR:ro, IND_RC_B+IND_RL_B:rw cost(4, 3).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
stbx GPR:ro, GPR:ro, GPR:ro cost(4, 3).
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
stfd FPR:ro, IND_RC_D+IND_RL_D:rw cost(4, 4).
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
stfdu FPR:ro, IND_RC_D:rw cost(4, 4).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
stfdx FPR:ro, GPR:ro, GPR:ro cost(4, 4).
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
stfs FSREG:ro, IND_RC_W+IND_RL_W:rw cost(4, 3).
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
stfsu FSREG:ro, IND_RC_W:rw cost(4, 3).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
stfsx FSREG:ro, GPR:ro, GPR:ro cost(4, 3).
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
sth GPR:ro, IND_RC_H+IND_RL_H:rw cost(4, 3).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
sthx GPR:ro, GPR:ro, GPR:ro cost(4, 3).
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
stw GPR:ro, IND_RC_W+IND_RL_W:rw cost(4, 3).
Add costs to powerpc instructions. Also show how andi., andis., or., set condition codes.
2016-10-17 18:57:21 +00:00
stwx GPR:ro, GPR:ro, GPR:ro cost(4, 3).
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
stwu GPR+LOCAL:ro, IND_RC_W:rw cost(4, 3).
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
xor GPR:wo, GPR:ro, GPR:ro.
xori GPR:wo, GPR:ro, CONST:ro.
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
xoris GPR:wo, GPR:ro, CONST:ro.
Remove the "invalid" stacking rule. When ncg fell back on this rule, it did emit the string "invalid" in the assembly code and caused a syntax error in the assembler. Adjust the stacking rules so we can stack LOCAL, CONST, and LABEL without falling back on the "invalid" rule, and so we can stack them when we have no free register except the scratch register.
2016-09-27 20:46:11 +00:00
Add assembler support for fixing up arbitrary oris/addi pairs of instructions; this should allow oris/lwz constant value loads, which will save an opcode.
2017-01-14 23:15:01 +00:00
comment "!" LABEL:ro cost(0, 0).
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
MOVES
from GPR to GPR
Use "mr" and make a few other tweaks in PowerPC ncg table. Use extended "mr" instead of basic "or" to move registers. Both "mr" and "or" encode the same machine instruction. With "mr", I can more easily search the assembly output for register moves. Fold several stacking rules into a single rule ANY_BHW-REG to STACK. Remove the EM patterns for loc mlu $2==2 and loc slu. The first pattern had the wrong size (should be $2==4, not $2==2). Both patterns were redundant. They rewrote loc mlu as loc mli and loc slu as loc sli, but this table doesn't have patterns for loc mli or loc sli, so it is enough to rewrite mlu as mli and slu as sli.
2017-02-10 16:45:50 +00:00
gen mr %2, %1
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
/* Constants */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
from CONST + CONST_STACK smalls(%val) to GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
COMMENT("move CONST->GPR smalls")
li %2, {CONST, %1.val}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
from CONST + CONST_STACK lo(%val)==0 to GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
COMMENT("move CONST->GPR shifted")
lis %2, {CONST, hi(%1.val)}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
from CONST + CONST_STACK to GPR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
COMMENT("move CONST->GPR")
lis %2, {CONST, hi(%1.val)}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
ori %2, %2, {CONST, lo(%1.val)}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
/* Can't use addi %2, %2, {CONST, los(%1.val)}
* because %2 might be R0. */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from LABEL to GPR
gen
COMMENT("move LABEL->GPR")
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
lis %2, {LABEL_HI, %1.adr}
ori %2, %2, {LABEL_LO, %1.adr}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
from LABEL_HA to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lis %2, %1
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Sign extension */
from SEX_B to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen extsb %2, %1.reg
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SEX_H to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen extsh %2, %1.reg
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Register + something */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
from SUM_RIS to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen addis %2, %1.reg, {CONST, %1.offhi}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SUM_RC to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen addi %2, %1.reg, {CONST, %1.off}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
from SUM_RL to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen addi %2, %1.reg, {LABEL_LO, %1.adr}
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from SUM_RR to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen add %2, %1.reg1, %1.reg2
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
/* Read byte */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from IND_RC_B+IND_RL_B to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lbz %2, %1
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from IND_RR_B to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lbzx %2, %1.reg1, %1.reg2
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
/* Write byte */
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from GPR to IND_RC_B+IND_RL_B
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen stb %1, %2
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from GPR to IND_RR_B
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen stbx %1, %2.reg1, %2.reg2
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
/* Read halfword (short) */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from IND_RC_H+IND_RL_H to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lhz %2, %1
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from IND_RR_H to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lhzx %2, %1.reg1, %1.reg2
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from IND_RC_H_S+IND_RL_H_S to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lha %2, %1
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from IND_RR_H_S to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lhax %2, %1.reg1, %1.reg2
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
/* Write halfword */
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from GPR to IND_RC_H+IND_RL_H
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen sth %1, %2
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
from GPR to IND_RR_H
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen sthx %1, %2.reg1, %2.reg2
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Read word */
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from IND_RC_W+IND_RL_W to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lwz %2, %1
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_RR_W to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lwzx %2, %1.reg1, %1.reg2
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from IND_RC_W+IND_RL_W to FSREG
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lfs %2, %1
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from IND_RR_W to FSREG
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lfsx %2, %1.reg1, %1.reg2
Remove IND_LABEL_W and IND_LABEL_D Because li32 always loads a label into a GPR, it is sufficient to coerce LABEL to REG, then use IND_RC_W or IND_RC_D for indirection through the label.
2016-10-16 20:33:24 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Write word */
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from GPR to IND_RC_W+IND_RL_W
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen stw %1, %2
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from GPR to IND_RR_W
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen stwx %1, %2.reg1, %2.reg2
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from FSREG to IND_RC_W+IND_RL_W
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen stfs %1, %2
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FSREG to IND_RR_W
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen stfsx %1, %2.reg1, %2.reg2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Read double */
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from IND_RC_D+IND_RL_D to FPR
gen lfd %2, %1
Simplify moves to and from IND_RC_* Now that SUM_RC always has a signed 16-bit constant, it happens that the various IND_RC_* tokens also have a signed 16-bit constant, so we no longer need to touch the scratch register.
2016-10-16 20:02:25 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from IND_RR_D to FPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen lfdx %2, %1.reg1, %1.reg2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Write double */
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
from FPR to IND_RC_D+IND_RL_D
gen stfd %1, %2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FPR to IND_RR_D
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen stfdx %1, %2.reg1, %2.reg2
Remove IND_LABEL_W and IND_LABEL_D Because li32 always loads a label into a GPR, it is sufficient to coerce LABEL to REG, then use IND_RC_W or IND_RC_D for indirection through the label.
2016-10-16 20:33:24 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Logicals */
from NOT_R to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen nor %2, %1.reg, %1.reg
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from AND_RR to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen and %2, %1.reg1, %1.reg2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from OR_RR to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen or %2, %1.reg1, %1.reg2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
from OR_RIS to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen oris %2, %1.reg, {CONST, %1.valhi}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from OR_RC to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen ori %2, %1.reg, {CONST, %1.val}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from XOR_RR to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen xor %2, %1.reg1, %1.reg2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
from XOR_RIS to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen xoris %2, %1.reg, {CONST, %1.valhi}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from XOR_RC to GPR
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen xori %2, %1.reg, {CONST, %1.val}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
/* Conditions */
/* Compare values, then copy cr0 to GPR. */
from COND_RC to GPR
gen
cmpwi %1.reg, {CONST, %1.val}
mfcr %2
from COND_RR to GPR
gen
cmpw %1.reg1, %1.reg2
mfcr %2
from CONDL_RC to GPR
gen
cmplwi %1.reg, {CONST, %1.val}
mfcr %2
from CONDL_RR to GPR
gen
cmplw %1.reg1, %1.reg2
mfcr %2
from COND_FS to GPR
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
fcmpo cr0, %1.reg1, %1.reg2
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
mfcr %2
from COND_FD to GPR
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
fcmpo cr0, %1.reg1, %1.reg2
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
mfcr %2
/* Given a copy of cr0 in %1.reg, extract a condition bit
* (lt, gt, eq) and perhaps flip it.
*/
from XEQ to GPR
gen
extrwi %2, %1.reg, {CONST, 1}, {CONST, 2}
from XNE to GPR
gen
extrwi %2, %1.reg, {CONST, 1}, {CONST, 2}
xori %2, %2, {CONST, 1}
from XGT to GPR
gen
extrwi %2, %1.reg, {CONST, 1}, {CONST, 1}
from XGE to GPR
gen
extrwi %2, %1.reg, {CONST, 1}, {CONST, 0}
xori %2, %2, {CONST, 1}
from XLT to GPR
gen
extrwi %2, %1.reg, {CONST, 1}, {CONST, 0}
from XLE to GPR
gen
extrwi %2, %1.reg, {CONST, 1}, {CONST, 1}
xori %2, %2, {CONST, 1}
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
/* GPRE exists solely to allow us to use regvar() (which can only be used in
an expression) as a register constant. */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
from ANY_BHW to GPRE
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %1, %2.reg
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
TESTS
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
/* Given orX %1, %1, %1, ncgg says, "Instruction destroys %1,
* not allowed here". We use orX_readonly to trick ncgg.
Use "mr" and make a few other tweaks in PowerPC ncg table. Use extended "mr" instead of basic "or" to move registers. Both "mr" and "or" encode the same machine instruction. With "mr", I can more easily search the assembly output for register moves. Fold several stacking rules into a single rule ANY_BHW-REG to STACK. Remove the EM patterns for loc mlu $2==2 and loc slu. The first pattern had the wrong size (should be $2==4, not $2==2). Both patterns were redundant. They rewrote loc mlu as loc mli and loc slu as loc sli, but this table doesn't have patterns for loc mli or loc sli, so it is enough to rewrite mlu as mli and slu as sli.
2017-02-10 16:45:50 +00:00
*
* Using "or." and not "mr." because mach/powerpc/top/table
* was optimizing "or." and not "mr.".
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
*/
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
to test GPR
gen
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
orX_readonly %1, %1, %1
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
STACKINGRULES
Remove the "invalid" stacking rule. When ncg fell back on this rule, it did emit the string "invalid" in the assembly code and caused a syntax error in the assembler. Adjust the stacking rules so we can stack LOCAL, CONST, and LABEL without falling back on the "invalid" rule, and so we can stack them when we have no free register except the scratch register.
2016-09-27 20:46:11 +00:00
from LOCAL to STACK
gen
COMMENT("stack LOCAL")
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
stwu %1, {IND_RC_W, sp, 0-4}
Remove the "invalid" stacking rule. When ncg fell back on this rule, it did emit the string "invalid" in the assembly code and caused a syntax error in the assembler. Adjust the stacking rules so we can stack LOCAL, CONST, and LABEL without falling back on the "invalid" rule, and so we can stack them when we have no free register except the scratch register.
2016-09-27 20:46:11 +00:00
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
from REG to STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
COMMENT("stack REG")
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
stwu %1, {IND_RC_W, sp, 0-4}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Use "mr" and make a few other tweaks in PowerPC ncg table. Use extended "mr" instead of basic "or" to move registers. Both "mr" and "or" encode the same machine instruction. With "mr", I can more easily search the assembly output for register moves. Fold several stacking rules into a single rule ANY_BHW-REG to STACK. Remove the EM patterns for loc mlu $2==2 and loc slu. The first pattern had the wrong size (should be $2==4, not $2==2). Both patterns were redundant. They rewrote loc mlu as loc mli and loc slu as loc sli, but this table doesn't have patterns for loc mli or loc sli, so it is enough to rewrite mlu as mli and slu as sli.
2017-02-10 16:45:50 +00:00
from ANY_BHW-REG to STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Use "mr" and make a few other tweaks in PowerPC ncg table. Use extended "mr" instead of basic "or" to move registers. Both "mr" and "or" encode the same machine instruction. With "mr", I can more easily search the assembly output for register moves. Fold several stacking rules into a single rule ANY_BHW-REG to STACK. Remove the EM patterns for loc mlu $2==2 and loc slu. The first pattern had the wrong size (should be $2==4, not $2==2). Both patterns were redundant. They rewrote loc mlu as loc mli and loc slu as loc sli, but this table doesn't have patterns for loc mli or loc sli, so it is enough to rewrite mlu as mli and slu as sli.
2017-02-10 16:45:50 +00:00
COMMENT("stack ANY_BHW-REG")
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
move %1, RSCRATCH
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
stwu RSCRATCH, {IND_RC_W, sp, 0-4}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_ALL_D to STACK
gen
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
COMMENT("stack IND_ALL_D")
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
move %1, FSCRATCH
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
stfdu FSCRATCH, {IND_RC_D, sp, 0-8}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
from FREG to STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("stack FPR")
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
stfdu %1, {IND_RC_D, sp, 0-8}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FSREG to STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("stack FSREG")
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
stfsu %1, {IND_RC_W, sp, 0-4}
Remove the "invalid" stacking rule. When ncg fell back on this rule, it did emit the string "invalid" in the assembly code and caused a syntax error in the assembler. Adjust the stacking rules so we can stack LOCAL, CONST, and LABEL without falling back on the "invalid" rule, and so we can stack them when we have no free register except the scratch register.
2016-09-27 20:46:11 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
COERCIONS
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
from ANY_BHW
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses REG
gen
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
COMMENT("coerce ANY_BHW->REG")
Remove most of GPRE from mach/powerpc/ncg/table We only need GPRE in a few places where we write {GPRE, regvar(...)} because ncgg can't parse plain regvar(...). In all other places, a plain GPR works. Also remove gpr_gpr_gpr and a few other unused and fake instructions from the list of instructions.
2016-10-07 02:59:27 +00:00
move %1, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from STACK
uses REG
gen
COMMENT("coerce STACK->REG")
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
lwz %a, {IND_RC_W, sp, 0}
addi sp, sp, {CONST, 4}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
from FSREG
uses FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fmr %a, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
from FREG
uses FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fmr %a, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from STACK
uses FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("coerce STACK->FREG")
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
lfd %a, {IND_RC_D, sp, 0}
addi sp, sp, {CONST, 8}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from STACK
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
uses FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
COMMENT("coerce STACK->FSREG")
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
lfs %a, {IND_RC_W, sp, 0}
addi sp, sp, {CONST, 4}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
yields %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_ALL_W
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
uses FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
move %1, %a
yields %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
/*
Remove REG_PAIR. I added REG_PAIR in cfbc537 to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commit c5bb3be, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
2017-02-13 23:11:27 +00:00
* from IND_RC_D to REG REG is not possible, because
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
* %1.off+4 might overflow a signed 16-bit integer in
Remove REG_PAIR. I added REG_PAIR in cfbc537 to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commit c5bb3be, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
2017-02-13 23:11:27 +00:00
* move {IND_RC_W, %1.val, %1.off+4}, %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
*/
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
from IND_ALL_D
uses FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
move %1, %a
yields %a
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
PATTERNS
/* Intrinsics */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
pat loc $1==(0-0x8000) /* Load constant */
yields {CONST_N8000, $1}
pat loc $1>=(0-0x7FFF) && $1<=(0-1)
yields {CONST_N7FFF_N0001, $1}
pat loc $1>=0 && $1<=0x7FFF
yields {CONST_0000_7FFF, $1}
pat loc $1==0x8000
yields {CONST_8000, $1}
pat loc $1>=0x8001 && $1<=0xFFFF
yields {CONST_8001_FFFF, $1}
pat loc lo($1)==0
yields {CONST_HZ, $1}
pat loc
yields {CONST_HL, $1}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dup $1==INT32 /* Duplicate word on top of stack */
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %1 %1
Add a rule for sdl ldl $1==$2 to work around a bug. In our powerpc table, sdl fails to kill the old value of the local. This is a bug, because a later ldl can load the old value instead of the newly stored value. By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl 0", the newly added rule works around the bug, but only when the ldl is immediately after the sdl. This rule improves code that uses double-precision floating point. The output of printf("%f", 6.0) in C changes from all zero digits to "6000000" but still doesn't print the decimal point. The result of atof("-123.456") becomes correct. In startrek, I can now move the Enterprise, but I still can't fire phasers without crashing the game. We already have a rule for stl lol $1==$2. We had two copies of the rule, so I am deleting the second copy.
2016-09-30 15:50:50 +00:00
with FSREG
yields %1 %1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dup $1==INT64 /* Duplicate double-word on top of stack */
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %2 %1 %2 %1
Add a rule for sdl ldl $1==$2 to work around a bug. In our powerpc table, sdl fails to kill the old value of the local. This is a bug, because a later ldl can load the old value instead of the newly stored value. By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl 0", the newly added rule works around the bug, but only when the ldl is immediately after the sdl. This rule improves code that uses double-precision floating point. The output of printf("%f", 6.0) in C changes from all zero digits to "6000000" but still doesn't print the decimal point. The result of atof("-123.456") becomes correct. In startrek, I can now move the Enterprise, but I still can't fire phasers without crashing the game. We already have a rule for stl lol $1==$2. We had two copies of the rule, so I am deleting the second copy.
2016-09-30 15:50:50 +00:00
with FREG
yields %1 %1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat exg $1==INT32 /* Exchange top two words on stack */
Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I can search for RSCRATCH without finding FSCRATCH. I also want to avoid confusion with the SCRATCH keyword of the old code generator (cg which came before ncg). Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH or any other GPR or FPR that isn't an allocatable REG or FREG. Then ncgg rejects any rule that tries to stack a GPR or FPR, so change such rules to stack a REG or FREG.
2016-10-07 00:47:42 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %1 %2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat stl lol $1==$2 /* Store then load local */
leaving
dup 4
stl $1
Add a rule for sdl ldl $1==$2 to work around a bug. In our powerpc table, sdl fails to kill the old value of the local. This is a bug, because a later ldl can load the old value instead of the newly stored value. By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl 0", the newly added rule works around the bug, but only when the ldl is immediately after the sdl. This rule improves code that uses double-precision floating point. The output of printf("%f", 6.0) in C changes from all zero digits to "6000000" but still doesn't print the decimal point. The result of atof("-123.456") becomes correct. In startrek, I can now move the Enterprise, but I still can't fire phasers without crashing the game. We already have a rule for stl lol $1==$2. We had two copies of the rule, so I am deleting the second copy.
2016-09-30 15:50:50 +00:00
pat sdl ldl $1==$2 /* Store then load double local */
leaving
dup 8
sdl $1
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lal sti lal loi $1==$3 && $2==$4 /* Store then load local, of a different size */
leaving
dup INT32
lal $1
sti $2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ste loe $1==$2 /* Store then load external */
leaving
dup 4
ste $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Type conversions */
pat loc loc ciu /* signed X -> unsigned X */
leaving
loc $1
loc $2
cuu
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cuu $1==$2 /* unsigned X -> unsigned X */
/* nop */
pat loc loc cii $1==$2 /* signed X -> signed X */
/* nop */
pat loc loc cui $1==$2 /* unsigned X -> signed X */
/* nop */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cui $1==INT8 && $2==INT32 /* unsigned char -> signed int */
/* nop */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cui $1==INT16 && $2==INT32 /* unsigned short -> signed int */
/* nop */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cii $1==INT8 && $2==INT32 /* signed char -> signed int */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {SEX_B, %1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cii $1==2 && $2==4 /* signed char -> signed short */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {SEX_H, %1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Local variables */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
pat lal smalls($1) /* Load address of local */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
yields {SUM_RC, fp, $1}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
pat lal /* Load address of local */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
uses REG={SUM_RIS, fp, his($1)}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
yields {SUM_RC, %a, los($1)}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lol inreg($1)>0 /* Load from local */
yields {LOCAL, $1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lol /* Load from local */
leaving
lal $1
loi INT32
pat ldl /* Load double-word from local */
leaving
lal $1
loi INT32*2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat stl inreg($1)>0 /* Store to local */
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
with ANY_BHW
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
kills regvar($1), LOCAL %off==$1
gen
move %1, {GPRE, regvar($1)}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat stl /* Store to local */
leaving
lal $1
sti INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sdl /* Store double-word to local */
leaving
lal $1
sti INT32*2
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lil inreg($1)>0 /* Load from indirected local */
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
yields {IND_RC_W, regvar($1), 0}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lil /* Load from indirected local */
leaving
lol $1
loi INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sil /* Save to indirected local */
leaving
lol $1
sti INT32
Add a rule for sdl ldl $1==$2 to work around a bug. In our powerpc table, sdl fails to kill the old value of the local. This is a bug, because a later ldl can load the old value instead of the newly stored value. By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl 0", the newly added rule works around the bug, but only when the ldl is immediately after the sdl. This rule improves code that uses double-precision floating point. The output of printf("%f", 6.0) in C changes from all zero digits to "6000000" but still doesn't print the decimal point. The result of atof("-123.456") becomes correct. In startrek, I can now move the Enterprise, but I still can't fire phasers without crashing the game. We already have a rule for stl lol $1==$2. We had two copies of the rule, so I am deleting the second copy.
2016-09-30 15:50:50 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zrl /* Zero local */
leaving
loc 0
stl $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat inl /* Increment local */
leaving
lol $1
loc 1
adi 4
stl $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat del /* Decrement local */
leaving
lol $1
loc 1
sbi 4
stl $1
/* Global variables */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lpi /* Load address of external function */
leaving
lae $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lae /* Load address of external */
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
uses REG={LABEL_HA, $1}
yields {SUM_RL, %a, $1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loe /* Load word external */
leaving
lae $1
loi INT32
pat ste /* Store word external */
leaving
lae $1
sti INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lde /* Load double-word external */
leaving
lae $1
loi INT64
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sde /* Store double-word external */
leaving
lae $1
sti INT64
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zre /* Zero external */
leaving
loc 0
ste $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ine /* Increment external */
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
leaving
loe $1
inc
ste $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dee /* Decrement external */
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
leaving
loe $1
dec
ste $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Structures */
pat lof /* Load word offsetted */
leaving
adp $1
loi INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ldf /* Load double-word offsetted */
leaving
adp $1
loi INT64
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat stf /* Store word offsetted */
leaving
adp $1
sti INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sdf /* Store double-word offsetted */
leaving
adp $1
sti INT64
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Loads and stores */
pat loi $1==INT8 /* Load byte indirect */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_B, %1, 0}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with exact SUM_RC
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_B, %1.reg, %1.off}
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
with exact SUM_RL
yields {IND_RL_B, %1.reg, %1.adr}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with exact SUM_RR
yields {IND_RR_B, %1.reg1, %1.reg2}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
pat loi loc loc cii $1==INT16 && $2==INT16 && $3==INT32
/* Load half-word indirect and sign extend */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_H_S, %1, 0}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with exact SUM_RC
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_H_S, %1.reg, %1.off}
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
with exact SUM_RL
yields {IND_RL_H_S, %1.reg, %1.adr}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with exact SUM_RR
yields {IND_RR_H_S, %1.reg1, %1.reg2}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loi $1==INT16 /* Load half-word indirect */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_H, %1, 0}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with exact SUM_RC
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
yields {IND_RC_H, %1.reg, %1.off}
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
with exact SUM_RL
yields {IND_RL_H, %1.reg, %1.adr}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with exact SUM_RR
yields {IND_RR_H, %1.reg1, %1.reg2}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loi $1==INT32 /* Load word indirect */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {IND_RC_W, %1, 0}
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
with exact SUM_RC
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {IND_RC_W, %1.reg, %1.off}
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
with exact SUM_RL
yields {IND_RL_W, %1.reg, %1.adr}
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
with exact SUM_RR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {IND_RR_W, %1.reg1, %1.reg2}
pat loi $1==INT64 /* Load double-word indirect */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {IND_RC_D, %1, 0}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with exact SUM_RC
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {IND_RC_D, %1.reg, %1.off}
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
with exact SUM_RL
yields {IND_RL_D, %1.reg, %1.adr}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with exact SUM_RR
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {IND_RR_D, %1.reg1, %1.reg2}
pat loi /* Load arbitrary size */
leaving
loc $1
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
los 4
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
pat los $1==4 /* Load arbitrary size */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
with REG STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
kills ALL
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move %1, r3
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
bl {LABEL, ".los4"}
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sti $1==INT8 /* Store byte indirect */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RC_B, %1, 0}
with SUM_RC REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RC_B, %1.reg, %1.off}
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
with SUM_RL REG
kills MEMORY
gen move %2, {IND_RL_B, %1.reg, %1.adr}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with SUM_RR REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RR_B, %1.reg1, %1.reg2}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sti $1==INT16 /* Store half-word indirect */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RC_H, %1, 0}
with SUM_RC REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RC_H, %1.reg, %1.off}
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
with SUM_RL REG
kills MEMORY
gen move %2, {IND_RL_H, %1.reg, %1.adr}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with SUM_RR REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RR_H, %1.reg1, %1.reg2}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sti $1==INT32 /* Store word indirect */
Use ha16/lo16 to emit pairs of lis/stw, lis/lfs, lis/stfs. A 4-byte load from a label yields a token IND_RL_W. This token emits either lis/lwz or lis/lfs, if we want a general-purpose register or a floating-point register.
2017-02-02 15:48:25 +00:00
with REG REG+FSREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RC_W, %1, 0}
with SUM_RC REG+FSREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RC_W, %1.reg, %1.off}
In PowerPC ncg, allocate register for ha16[label]. Use it to generate code like lis r12,ha16[__II0] lis r11,ha16[_f] lfs f1,lo16[_f](r11) lfs f2,lo16[__II0](r12) fadds f13,f2,f1 stfs f13,lo16[_f](r11) Here ncg has allocated r11 for ha16[_f]. We use r11 in lfs and again in stfs. Before this change, we needed an extra lis before stfs, because ncg did not remember that ha16[_f] was in a register. This example has a gap between ha16[__II0] and lo16[__II0], because the lo16 is not in the next instruction. This requires my previous commit 1bf58cf for RELOLIS. There is a gap because ncg emits the lis as soon as I allocate it. The "lfs f2,lo16[__II0](r12)" happens in a coercion from IND_RL_W to FSREG. The coercion allocates one FSREG but may not allocate any other registers. So I must allocate r12 earlier. I allocate r12 in pat lae, but this causes a gap.
2017-02-08 17:23:06 +00:00
with SUM_RL REG+FSREG
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RL_W, %1.reg, %1.adr}
with SUM_RR REG+FSREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RR_W, %1.reg1, %1.reg2}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sti $1==INT64 /* Store double-word indirect */
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
with REG FREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RC_D, %1, 0}
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with SUM_RC FREG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
gen move %2, {IND_RC_D, %1.reg, %1.off}
Use ha16/lo16 to load or store 1, 2, 8 bytes from labels. Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
2017-02-08 17:31:14 +00:00
with SUM_RL FREG
kills MEMORY
gen move %2, {IND_RL_D, %1.reg, %1.adr}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with SUM_RR FREG
kills MEMORY
gen move %2, {IND_RR_D, %1.reg1, %1.reg2}
Remove REG_PAIR. I added REG_PAIR in cfbc537 to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commit c5bb3be, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
2017-02-13 23:11:27 +00:00
with REG REG REG
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Remove REG_PAIR. I added REG_PAIR in cfbc537 to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commit c5bb3be, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
2017-02-13 23:11:27 +00:00
move %2, {IND_RC_W, %1, 0}
move %3, {IND_RC_W, %1, 4}
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
/*
* Next 2 patterns exist because there is no coercion
Remove REG_PAIR. I added REG_PAIR in cfbc537 to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commit c5bb3be, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
2017-02-13 23:11:27 +00:00
* from IND_ALL_D to REG REG.
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
*/
with REG IND_RC_D
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
kills MEMORY
Remove REG_PAIR. I added REG_PAIR in cfbc537 to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commit c5bb3be, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
2017-02-13 23:11:27 +00:00
uses REG={SUM_RC, %2.reg, %2.off}, REG, REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Remove REG_PAIR. I added REG_PAIR in cfbc537 to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commit c5bb3be, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
2017-02-13 23:11:27 +00:00
move {IND_RC_W, %a, 0}, %b
move {IND_RC_W, %a, 4}, %c
move %b, {IND_RC_W, %1, 0}
move %c, {IND_RC_W, %1, 4}
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
with REG IND_RR_D
kills MEMORY
Remove REG_PAIR. I added REG_PAIR in cfbc537 to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commit c5bb3be, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
2017-02-13 23:11:27 +00:00
uses REG={SUM_RR, %2.reg1, %2.reg2}, REG, REG
In powerpc ncg, add a speed hack for sti 8. ncg is too slow with this many registers. A stack pattern "with GPR GPR GPR" or "with REG REG REG" takes too long to pick registers, causing ncg 8 to take about 2 seconds on each sti 8. I introduce REG_PAIR and there are only 4 such pairs. For programs that use sti 8 (including C programs that copy 8-byte structs), this speed hack improves the ncg run from several seconds to almost instantaneous. Also add a few COMMENT(...) lines in stacking rules.
2016-10-18 00:31:59 +00:00
gen
Remove REG_PAIR. I added REG_PAIR in cfbc537 to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commit c5bb3be, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
2017-02-13 23:11:27 +00:00
move {IND_RC_W, %a, 0}, %b
move {IND_RC_W, %a, 4}, %c
move %b, {IND_RC_W, %1, 0}
move %c, {IND_RC_W, %1, 4}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sti /* Store arbitrary size */
leaving
loc $1
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
sts 4
Add "kills MEMORY" to powerpc sti rules. Adjust some of the loi rules (and associated moves) so we can identify the tokens that must be in MEMORY. With this commit, I can navigate the Enterprise even if I comment out my work-around from e22c888.
2016-10-16 22:13:39 +00:00
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
pat sts $1==4 /* Store arbitrary size */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
with REG STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
kills ALL
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move %1, r3
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
bl {LABEL, ".sts4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Arithmetic wrappers */
pat ads $1==4 /* Add var to pointer */
leaving adi $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbs $1==4 /* Subtract var from pointer */
leaving sbi $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat adp /* Add constant to pointer */
leaving
loc $1
adi 4
pat adu /* Add unsigned */
leaving
adi $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbu /* Subtract unsigned */
leaving
sbi $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat inc /* Add 1 */
leaving
loc 1
adi 4
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dec /* Subtract 1 */
leaving
loc 1
sbi 4
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Use "mr" and make a few other tweaks in PowerPC ncg table. Use extended "mr" instead of basic "or" to move registers. Both "mr" and "or" encode the same machine instruction. With "mr", I can more easily search the assembly output for register moves. Fold several stacking rules into a single rule ANY_BHW-REG to STACK. Remove the EM patterns for loc mlu $2==2 and loc slu. The first pattern had the wrong size (should be $2==4, not $2==2). Both patterns were redundant. They rewrote loc mlu as loc mli and loc slu as loc sli, but this table doesn't have patterns for loc mli or loc sli, so it is enough to rewrite mlu as mli and slu as sli.
2017-02-10 16:45:50 +00:00
pat mlu /* Multiply unsigned */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
leaving
mli $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Use "mr" and make a few other tweaks in PowerPC ncg table. Use extended "mr" instead of basic "or" to move registers. Both "mr" and "or" encode the same machine instruction. With "mr", I can more easily search the assembly output for register moves. Fold several stacking rules into a single rule ANY_BHW-REG to STACK. Remove the EM patterns for loc mlu $2==2 and loc slu. The first pattern had the wrong size (should be $2==4, not $2==2). Both patterns were redundant. They rewrote loc mlu as loc mli and loc slu as loc sli, but this table doesn't have patterns for loc mli or loc sli, so it is enough to rewrite mlu as mli and slu as sli.
2017-02-10 16:45:50 +00:00
pat slu /* Shift left unsigned */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
leaving
sli $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Word arithmetic */
pat adi $1==4 /* Add word (second + top) */
with REG REG
yields {SUM_RR, %1, %2}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST2 REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {SUM_RC, %2, %1.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG CONST2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {SUM_RC, %1, %2.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_HZ REG
uses reusing %2, REG={SUM_RIS, %2, his(%1.val)}
yields %a
with REG CONST_HZ
uses reusing %1, REG={SUM_RIS, %1, his(%2.val)}
yields %a
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
with CONST_STACK-CONST2-CONST_HZ REG
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %2, REG={SUM_RIS, %2, his(%1.val)}
yields {SUM_RC, %a, los(%1.val)}
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
with REG CONST_STACK-CONST2-CONST_HZ
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %1, REG={SUM_RIS, %1, his(%2.val)}
yields {SUM_RC, %a, los(%2.val)}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbi $1==4 /* Subtract word (second - top) */
with REG REG
uses reusing %2, REG
gen
subf %a, %1, %2
yields %a
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST2_WHEN_NEG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {SUM_RC, %2, 0-%1.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_HZ REG
uses reusing %2, REG={SUM_RIS, %2, his(0-%1.val)}
yields %a
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
with CONST_STACK-CONST2_WHEN_NEG-CONST_HZ REG
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %2, REG={SUM_RIS, %2, his(0-%1.val)}
yields {SUM_RC, %a, los(0-%1.val)}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ngi $1==4 /* Negate word */
with REG
uses reusing %1, REG
gen
neg %a, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat mli $1==4 /* Multiply word (second * top) */
with REG REG
uses reusing %2, REG
gen
mullw %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dvi $1==4 /* Divide word (second / top) */
with REG REG
uses reusing %2, REG
gen
divw %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dvu $1==4 /* Divide unsigned word (second / top) */
with REG REG
uses reusing %2, REG
gen
divwu %a, %2, %1
yields %a
pat rmi $1==4 /* Remainder word (second % top) */
with REG REG
uses REG
gen
divw %a, %2, %1
mullw %a, %a, %1
subf %a, %a, %2
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat rmu $1==4 /* Remainder unsigned word (second % top) */
with REG REG
uses REG
gen
divwu %a, %2, %1
mullw %a, %a, %1
subf %a, %a, %2
yields %a
pat and $1==4 /* AND word */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG NOT_R
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
andc %a, %1, %2.reg
yields %a
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with NOT_R REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
andc %a, %2, %1.reg
yields %a
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {AND_RR, %1, %2}
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG UCONST2
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %1, REG
gen
andiX %a, %1, {CONST, %2.val}
yields %a
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with UCONST2 REG
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %2, REG
gen
andiX %a, %2, {CONST, %1.val}
yields %a
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG CONST_HZ
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %1, REG
gen
andisX %a, %1, {CONST, hi(%2.val)}
yields %a
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with CONST_HZ REG
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %2, REG
gen
andisX %a, %2, {CONST, hi(%1.val)}
yields %a
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat and defined($1) /* AND set */
Add a bunch more set operations to the PowerPC backends, and the Pascal test for the same.
2017-01-17 21:31:38 +00:00
leaving
loc $1
cal ".and"
pat and !defined($1)
leaving
cal ".and"
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ior $1==4 /* OR word */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG NOT_R
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
orc %a, %1, %2.reg
yields %a
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with NOT_R REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
orc %a, %2, %1.reg
yields %a
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {OR_RR, %1, %2}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG UCONST2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {OR_RC, %1, %2.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with UCONST2 REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {OR_RC, %2, %1.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG CONST_HZ
uses reusing %1, REG={OR_RIS, %1, hi(%2.val)}
yields %a
with CONST_HZ REG
uses reusing %2, REG={OR_RIS, %2, hi(%1.val)}
yields %a
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
with REG CONST_STACK-UCONST2-CONST_HZ
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %1, REG={OR_RIS, %1, hi(%2.val)}
yields {OR_RC, %1, lo(%2.val)}
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
with CONST_STACK-UCONST2-CONST_HZ REG
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %2, REG={OR_RIS, %2, hi(%1.val)}
yields {OR_RC, %2, lo(%1.val)}
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat ior defined($1) /* OR set */
Add a test (currently failing) to check that Pascal char sets can store all 256 possible values. Add the PowerPC ncg and mcg backend support to let the test actually run, including modifying a bunch of PowrePC libem functions so that they can be called from both ncg and mcg.
2017-01-15 21:28:14 +00:00
leaving
loc $1
cal ".ior"
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
/* OR set (variable), used in lang/m2/libm2/LtoUset.e */
pat ior !defined($1)
Add a test (currently failing) to check that Pascal char sets can store all 256 possible values. Add the PowerPC ncg and mcg backend support to let the test actually run, including modifying a bunch of PowrePC libem functions so that they can be called from both ncg and mcg.
2017-01-15 21:28:14 +00:00
leaving
cal ".ior"
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat xor $1==4 /* XOR word */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {XOR_RR, %1, %2}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG UCONST2
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {XOR_RC, %1, %2.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with UCONST2 REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {XOR_RC, %2, %1.val}
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with REG CONST_HZ
uses reusing %1, REG={XOR_RIS, %1, hi(%2.val)}
yields %a
with CONST_HZ REG
uses reusing %2, REG={XOR_RIS, %2, hi(%1.val)}
yields %a
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
with REG CONST_STACK-UCONST2-CONST_HZ
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %1, REG={XOR_RIS, %1, hi(%2.val)}
yields {XOR_RC, %1, lo(%2.val)}
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
with CONST_STACK-UCONST2-CONST_HZ REG
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
uses reusing %2, REG={XOR_RIS, %2, hi(%1.val)}
yields {XOR_RC, %2, lo(%1.val)}
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat xor defined($1) /* XOR set */
Edit PowerPC assembly for .and, .cms, .ior, .xor, .zer Remove one addi instruction from some loops. These loops had increased 2 pointers, they now increase 1 index. I must initialize the index, so I add "li r6, 0" before each loop. Change .zer to use subf instead of neg, add. Change .xor to take the size on the real stack, as .and and .or have done since 81c677d.
2017-02-11 23:00:56 +00:00
leaving
loc $1
cal ".xor"
pat xor !defined($1)
leaving
cal ".xor"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat com $1==INT32 /* NOT word */
with AND_RR
uses REG
gen
nand %a, %1.reg1, %1.reg2
yields %a
with OR_RR
uses REG
gen
nor %a, %1.reg1, %1.reg2
yields %a
with XOR_RR
uses REG
gen
eqv %a, %1.reg1, %1.reg2
yields %a
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields {NOT_R, %1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat com defined($1) /* NOT set */
Add a bunch more set operations to the PowerPC backends, and the Pascal test for the same.
2017-01-17 21:31:38 +00:00
leaving
loc $1
cal ".com"
pat com !defined($1)
leaving
cal ".com"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat zer $1==4 /* Push zero */
leaving
loc 0
Add a test (currently failing) to check that Pascal char sets can store all 256 possible values. Add the PowerPC ncg and mcg backend support to let the test actually run, including modifying a bunch of PowrePC libem functions so that they can be called from both ncg and mcg.
2017-01-15 21:28:14 +00:00
pat zer defined($1) /* Create empty set */
leaving
loc $1
cal ".zer"
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sli $1==4 /* Shift left (second << top) */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with CONST_STACK REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
rlwinm %a, %2, {CONST, (%1.val & 0x1F)}, {CONST, 0}, {CONST, 31-(%1.val & 0x1F)}
yields %a
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
slw %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sri $1==4 /* Shift right signed (second >> top) */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with CONST_STACK REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
srawi %a, %2, {CONST, %1.val & 0x1F}
yields %a
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
sraw %a, %2, %1
yields %a
pat sru $1==4 /* Shift right unsigned (second >> top) */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with CONST_STACK REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
rlwinm %a, %2, {CONST, 32-(%1.val & 0x1F)}, {CONST, (%1.val & 0x1F)}, {CONST, 31}
yields %a
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %2, REG
gen
srw %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Arrays */
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
pat aar $1==4 /* Address of array element */
leaving
cal ".aar4"
pat lar $1==4 /* Load from array */
with STACK
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
bl {LABEL, ".aar4"}
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
/* pass r3 = size from .aar4 to .los4 */
bl {LABEL, ".los4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
pat lae lar $2==4 && nicesize(rom($1, 3))
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
leaving
lae $1
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
aar 4
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
loi rom($1, 3)
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
pat sar $1==4 /* Store to array */
with STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
kills ALL
gen
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
bl {LABEL, ".aar4"}
/* pass r3 = size from .aar4 to .sts4 */
bl {LABEL, ".sts4"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
pat lae sar $2==4 && nicesize(rom($1, 3))
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
leaving
lae $1
Use .los4 in lar 4 and .sts4 in sar 4. Our libem had two implementations of loading a block from a stack, one for lar 4 and one for los 4. Now lar 4 and los 4 share the code in .los4. Likewise, sar 4 and sts 4 share the code in .sts4. Rename .los to .los4 and .sts to .sts4, because they implement los 4 and sts 4. Remove the special case for loading or storing 4 bytes, because we can do it with 1 iteration of the loop. Remove the lines to "align size" where the size must already be a multiple of 4. Fix the upper bound check in .aar4. Change .aar4, .lar4, .los4, .sar4, .sts4 to pass all operands on the real stack, except that .los4 and .sts4 take the size in register r3. Have .aar4 set r3 to the size of the array element. So lar 4 is just .aar4 then .los4, and sar 4 is just .aar4 then .sts4. ncg no longer calls .lar4 and .sar4 in libem, because it inlines the code; but I keep .lar4 and .sar4 in libem, because mcg references them. They might or might not work in mcg.
2017-02-13 20:22:00 +00:00
aar 4
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
sti rom($1, 3)
/* Sets */
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat set defined($1) /* Create singleton set */
Add a test (currently failing) to check that Pascal char sets can store all 256 possible values. Add the PowerPC ncg and mcg backend support to let the test actually run, including modifying a bunch of PowrePC libem functions so that they can be called from both ncg and mcg.
2017-01-15 21:28:14 +00:00
leaving
loc $1
cal ".set"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
/* Create set (variable), used in lang/m2/libm2/LtoUset.e */
pat set !defined($1)
Add a test (currently failing) to check that Pascal char sets can store all 256 possible values. Add the PowerPC ncg and mcg backend support to let the test actually run, including modifying a bunch of PowrePC libem functions so that they can be called from both ncg and mcg.
2017-01-15 21:28:14 +00:00
leaving
cal ".set"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
pat inn defined($1) /* Test for set bit */
Add a test (currently failing) to check that Pascal char sets can store all 256 possible values. Add the PowerPC ncg and mcg backend support to let the test actually run, including modifying a bunch of PowrePC libem functions so that they can be called from both ncg and mcg.
2017-01-15 21:28:14 +00:00
leaving
loc $1
cal ".inn"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add a bunch more set operations to the PowerPC backends, and the Pascal test for the same.
2017-01-17 21:31:38 +00:00
pat inn !defined($1)
leaving
cal ".inn"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Boolean resolutions */
pat teq /* top = (top == 0) */
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
test %1
mfcr %a
move {XEQ, %a}, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat tne /* top = (top != 0) */
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
test %1
mfcr %a
move {XNE, %a}, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat tlt /* top = (top < 0) */
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
test %1
mfcr %a
move {XLT, %a}, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat tle /* top = (top <= 0) */
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
test %1
mfcr %a
move {XLE, %a}, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat tgt /* top = (top > 0) */
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
test %1
mfcr %a
move {XGT, %a}, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
pat tge /* top = (top >= 0) */
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, REG
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
test %1
mfcr %a
move {XGE, %a}, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmi teq $1==4 /* Signed second == top */
with REG CONST2
uses reusing %1, REG={COND_RC, %1, %2.val}
gen move {XEQ, %a}, %a
yields %a
with CONST2 REG
uses reusing %1, REG={COND_RC, %2, %1.val}
gen move {XEQ, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={COND_RR, %2, %1}
gen move {XEQ, %a}, %a
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmi tne $1==4 /* Signed second != top */
with REG CONST2
uses reusing %1, REG={COND_RC, %1, %2.val}
gen move {XNE, %a}, %a
yields %a
with CONST2 REG
uses reusing %1, REG={COND_RC, %2, %1.val}
gen move {XNE, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={COND_RR, %2, %1}
gen move {XNE, %a}, %a
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmi tgt $1==4 /* Signed second > top */
with REG CONST2
uses reusing %1, REG={COND_RC, %1, %2.val}
gen move {XLT, %a}, %a
yields %a
with CONST2 REG
uses reusing %1, REG={COND_RC, %2, %1.val}
gen move {XGT, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={COND_RR, %2, %1}
gen move {XGT, %a}, %a
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmi tge $1==4 /* Signed second >= top */
with REG CONST2
uses reusing %1, REG={COND_RC, %1, %2.val}
gen move {XLE, %a}, %a
yields %a
with CONST2 REG
uses reusing %1, REG={COND_RC, %2, %1.val}
gen move {XGE, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={COND_RR, %2, %1}
gen move {XGE, %a}, %a
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmi tlt $1==4 /* Signed second < top */
with REG CONST2
uses reusing %1, REG={COND_RC, %1, %2.val}
gen move {XGT, %a}, %a
yields %a
with CONST2 REG
uses reusing %1, REG={COND_RC, %2, %1.val}
gen move {XLT, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={COND_RR, %2, %1}
gen move {XLT, %a}, %a
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmi tle $1==4 /* Signed second <= top */
with REG CONST2
uses reusing %1, REG={COND_RC, %1, %2.val}
gen move {XGE, %a}, %a
yields %a
with CONST2 REG
uses reusing %1, REG={COND_RC, %2, %1.val}
gen move {XLE, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={COND_RR, %2, %1}
gen move {XLE, %a}, %a
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmu teq $1==4 /* Unsigned second == top */
with REG UCONST2
uses reusing %1, REG={CONDL_RC, %1, %2.val}
gen move {XEQ, %a}, %a
yields %a
with UCONST2 REG
uses reusing %1, REG={CONDL_RC, %2, %1.val}
gen move {XEQ, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={CONDL_RR, %2, %1}
gen move {XEQ, %a}, %a
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmu tne $1==4 /* Unsigned second != top */
with REG UCONST2
uses reusing %1, REG={CONDL_RC, %1, %2.val}
gen move {XNE, %a}, %a
yields %a
with UCONST2 REG
uses reusing %1, REG={CONDL_RC, %2, %1.val}
gen move {XNE, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={CONDL_RR, %2, %1}
gen move {XNE, %a}, %a
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmu tgt $1==4 /* Unsigned second > top */
with REG UCONST2
uses reusing %1, REG={CONDL_RC, %1, %2.val}
gen move {XLT, %a}, %a
yields %a
with UCONST2 REG
uses reusing %1, REG={CONDL_RC, %2, %1.val}
gen move {XGT, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={CONDL_RR, %2, %1}
gen move {XGT, %a}, %a
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmu tge $1==4 /* Unsigned second >= top */
with REG UCONST2
uses reusing %1, REG={CONDL_RC, %1, %2.val}
gen move {XLE, %a}, %a
yields %a
with UCONST2 REG
uses reusing %1, REG={CONDL_RC, %2, %1.val}
gen move {XGE, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={CONDL_RR, %2, %1}
gen move {XGE, %a}, %a
yields %a
pat cmu tlt $1==4 /* Unsigned second < top */
with REG UCONST2
uses reusing %1, REG={CONDL_RC, %1, %2.val}
gen move {XGT, %a}, %a
yields %a
with UCONST2 REG
uses reusing %1, REG={CONDL_RC, %2, %1.val}
gen move {XLT, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={CONDL_RR, %2, %1}
gen move {XLT, %a}, %a
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
pat cmu tle $1==4 /* Unsigned second <= top */
with REG UCONST2
uses reusing %1, REG={CONDL_RC, %1, %2.val}
gen move {XGE, %a}, %a
yields %a
with UCONST2 REG
uses reusing %1, REG={CONDL_RC, %2, %1.val}
gen move {XLE, %a}, %a
yields %a
with REG REG
uses reusing %1, REG={CONDL_RR, %2, %1}
gen move {XLE, %a}, %a
yields %a
/* Simple branches */
proc zxx example zeq
with REG STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
test %1
bxx* {LABEL, $1}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
/* Pop signed int, branch if... */
pat zeq call zxx("beq") /* top == 0 */
pat zne call zxx("bne") /* top != 0 */
pat zgt call zxx("bgt") /* top > 0 */
pat zge call zxx("bge") /* top >= 0 */
pat zlt call zxx("blt") /* top < 0 */
pat zle call zxx("ble") /* top >= 0 */
/* The peephole optimizer rewrites
* cmi 4 zeq
* as beq, and does same for bne, bgt, and so on.
*/
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
proc bxx example beq
with REG CONST2 STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
cmpwi %1, {CONST, %2.val}
bxx[2] {LABEL, $1}
with CONST2 REG STACK
gen
cmpwi %2, {CONST, %1.val}
bxx[1] {LABEL, $1}
with REG REG STACK
gen
cmpw %2, %1
bxx[1] {LABEL, $1}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
/* Pop two signed ints, branch if... */
pat beq call bxx("beq", "beq") /* second == top */
pat bne call bxx("bne", "bne") /* second != top */
pat bgt call bxx("bgt", "blt") /* second > top */
pat bge call bxx("bge", "ble") /* second >= top */
pat blt call bxx("blt", "bgt") /* second < top */
pat ble call bxx("ble", "bge") /* second >= top */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
proc cmu4zxx example cmu zeq
with REG CONST2 STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
cmplwi %1, {CONST, %2.val}
bxx[2] {LABEL, $2}
with CONST2 REG STACK
gen
cmplwi %2, {CONST, %1.val}
bxx[1] {LABEL, $2}
with REG REG STACK
gen
cmplw %2, %1
bxx[1] {LABEL, $2}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
/* Pop two unsigned ints, branch if... */
pat cmu zeq $1==4 call cmu4zxx("beq", "beq")
pat cmu zne $1==4 call cmu4zxx("bne", "bne")
pat cmu zgt $1==4 call cmu4zxx("bgt", "blt")
pat cmu zge $1==4 call cmu4zxx("bge", "ble")
pat cmu zlt $1==4 call cmu4zxx("blt", "bgt")
pat cmu zle $1==4 call cmu4zxx("ble", "bge")
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
/* Comparisons */
/* Each comparison extracts the lt and gt bits from cr0.
* extlwi %a, %a, 2, 0
* puts lt in the sign bit, so lt yields a negative result,
* gt yields positive.
* rlwinm %a, %a, 1, 31, 0
* puts gt in the sign bit, to reverse the comparison.
*/
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
pat cmi $1==INT32 /* Signed tristate compare */
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
with REG CONST2
uses reusing %1, REG={COND_RC, %1, %2.val}
gen rlwinm %a, %a, {CONST, 1}, {CONST, 31}, {CONST, 0}
yields %a
with CONST2 REG
uses reusing %2, REG={COND_RC, %2, %1.val}
gen extlwi %a, %a, {CONST, 2}, {CONST, 0}
yields %a
with REG REG
uses reusing %1, REG={COND_RR, %2, %1}
gen extlwi %a, %a, {CONST, 2}, {CONST, 0}
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add some missing clauses to los, sts, aar, inn, cmi, cmu. We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes other than 4. Add clause $1==4. We only implement inn when defined($1). The rule for aar needs 'kills ALL' because it kills many registers, like other rules that call libem.
2016-12-10 00:49:50 +00:00
pat cmu $1==INT32 /* Unsigned tristate compare */
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
with REG UCONST2
uses reusing %1, REG={CONDL_RC, %1, %2.val}
gen rlwinm %a, %a, {CONST, 1}, {CONST, 31}, {CONST, 0}
yields %a
with UCONST2 REG
uses reusing %2, REG={CONDL_RC, %2, %1.val}
gen extlwi %a, %a, {CONST, 2}, {CONST, 0}
yields %a
with REG REG
uses reusing %1, REG={CONDL_RR, %2, %1}
gen extlwi %a, %a, {CONST, 2}, {CONST, 0}
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat cmp /* Compare pointers */
leaving
cmu INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat cms $1==INT32 /* Compare blocks (word sized) */
leaving
cmi INT32
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add Modula-2 set operations to PowerPC ncg. This provides and, ior, xor, com, zer, set, cms when defined($1) and ior, set when !defined($1). I don't provide the other operations !defined($1) because our Modula-2 compiler hasn't used them. I wrote a Modula-2 example in https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788 Put a dummy comment in mach/powerpc/libem/build.lua so git checkout will touch that file. Without the touch, the build system doesn't see the new *.s files.
2016-12-10 17:23:07 +00:00
pat cms defined($1)
Add pat cms !defined($1) Switch .cms to pass inputs and outputs on the real stack, not in registers; like we do with .and, .or (81c677d) and .xor (c578c49). At this point, nearly all functions in libem use the real stack, not registers, for passing inputs and outputs. This simplifies the ncg table (which needs fewer lists of specific registers) but slows calls to libem. For example, after ba9b021, each call to .aar4 is about 10 instructions slower. I moved 3 inputs and 1 output from registers to the real stack. A program would take 4 instructions to move registers to stack, 4 to move stack to registers, and perhaps 2 to adjust the stack pointer.
2017-02-13 21:52:32 +00:00
leaving
loc $1
cal ".cms"
pat cms !defined($1)
leaving
cal ".cms"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Other branching and labelling */
pat lab topeltsize($1)==4 && !fallthrough($1)
Add constraints for pat lab, as done in the m68020 table. Always use 'kills ALL' when reaching a label, because our registers and tokens have the wrong values if the program jumps to this label from somewhere else. When falling through a label, if the top element is in r3, then require that the rest of the stack is in the real STACK, not in registers or tokens. I'm doing this to be certain that the missing constraints are not causing bugs. I did not find any such bug, perhaps because the labels are usually near other instructions (like conditional branches and function calls) that stack or kill tokens.
2017-01-24 16:26:35 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
labeldef $1
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
yields r3
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lab topeltsize($1)==4 && fallthrough($1)
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
with REG STACK
Add constraints for pat lab, as done in the m68020 table. Always use 'kills ALL' when reaching a label, because our registers and tokens have the wrong values if the program jumps to this label from somewhere else. When falling through a label, if the top element is in r3, then require that the rest of the stack is in the real STACK, not in registers or tokens. I'm doing this to be certain that the missing constraints are not causing bugs. I did not find any such bug, perhaps because the labels are usually near other instructions (like conditional branches and function calls) that stack or kill tokens.
2017-01-24 16:26:35 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move %1, r3
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
labeldef $1
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
yields r3
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lab topeltsize($1)!=4
with STACK
kills ALL
gen
labeldef $1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat bra topeltsize($1)==4 /* Unconditional jump with TOS GPRister */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
with REG STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move %1, r3
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
b {LABEL, $1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat bra topeltsize($1)!=4 /* Unconditional jump without TOS GPRister */
with STACK
gen
b {LABEL, $1}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Miscellaneous */
pat cal /* Call procedure */
with STACK
kills ALL
gen
bl {LABEL, $1}
pat cai /* Call procedure indirect */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
kills ALL
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
mtspr ctr, %1
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
bctrl.
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lfr $1==INT32 /* Load function result, word */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
yields r3
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lfr $1==INT64 /* Load function result, double-word */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
yields r4 r3
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ret $1==0 /* Return from procedure */
gen
return
b {LABEL, ".ret"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ret $1==INT32 /* Return from procedure, word */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move %1, r3
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
return
b {LABEL, ".ret"}
pat ret $1==INT64 /* Return from procedure, double-word */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
with REG REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move %1, r3
move %2, r4
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
return
b {LABEL, ".ret"}
pat blm /* Block move constant length */
Implement blm and bls using an inline loop. This replaces a call to memmove() in libc. That was working for me, but it can fail because EM programs don't always link to libc. blm and bls only need to copy aligned words. They don't need to copy bytes, and they don't need to copy between overlapping buffers, as memmove() does. So the new loop is simpler than memmove().
2017-02-12 00:30:12 +00:00
leaving
loc $1
bls
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat bls /* Block move variable length */
Implement blm and bls using an inline loop. This replaces a call to memmove() in libc. That was working for me, but it can fail because EM programs don't always link to libc. blm and bls only need to copy aligned words. They don't need to copy bytes, and they don't need to copy between overlapping buffers, as memmove() does. So the new loop is simpler than memmove().
2017-02-12 00:30:12 +00:00
with REG REG REG
uses reusing %1, REG, REG={CONST_0000_7FFF, 0}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Implement blm and bls using an inline loop. This replaces a call to memmove() in libc. That was working for me, but it can fail because EM programs don't always link to libc. blm and bls only need to copy aligned words. They don't need to copy bytes, and they don't need to copy between overlapping buffers, as memmove() does. So the new loop is simpler than memmove().
2017-02-12 00:30:12 +00:00
/* Wrong if size is zero */
srwi %1, %1, {CONST, 2}
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
mtspr ctr, %1
Implement blm and bls using an inline loop. This replaces a call to memmove() in libc. That was working for me, but it can fail because EM programs don't always link to libc. blm and bls only need to copy aligned words. They don't need to copy bytes, and they don't need to copy between overlapping buffers, as memmove() does. So the new loop is simpler than memmove().
2017-02-12 00:30:12 +00:00
1:
lwzx %a, %3, %b
stwx %a, %2, %b
addi %b, %b, {CONST, 4}
bdnz {LABEL, "1b"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat csa /* Array-lookup switch */
Made csa and csb work with mcg; adjust the libem functions and the corresponding invocation in the ncg table so the same helpers can be used for both mcg and ncg. Add a new IR opcode, FARJUMP, which jumps to a helper function but saves volatile registers.
2016-11-19 09:55:41 +00:00
with STACK
Add missing instances of "kills ALL" or "with STACK".
2017-02-13 21:38:26 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
b {LABEL, ".csa"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat csb /* Table-lookup switch */
Made csa and csb work with mcg; adjust the libem functions and the corresponding invocation in the ncg table so the same helpers can be used for both mcg and ncg. Add a new IR opcode, FARJUMP, which jumps to a helper function but saves volatile registers.
2016-11-19 09:55:41 +00:00
with STACK
Add missing instances of "kills ALL" or "with STACK".
2017-02-13 21:38:26 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
b {LABEL, ".csb"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* EM specials */
pat fil /* Set current filename */
leaving
lae $1
Remove .linenumber and .filename; use hol0 and hol0+4. We need this because some .e files in lang/ are using 'loe 0' and 'lae 4' to load the line number from hol0 and filename from hol0+4.
2016-09-30 17:40:36 +00:00
ste "hol0+4"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lin /* Set current line number */
leaving
loc $1
Remove .linenumber and .filename; use hol0 and hol0+4. We need this because some .e files in lang/ are using 'loe 0' and 'lae 4' to load the line number from hol0 and filename from hol0+4.
2016-09-30 17:40:36 +00:00
ste "hol0"
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lni /* Increment line number */
leaving
Remove .linenumber and .filename; use hol0 and hol0+4. We need this because some .e files in lang/ are using 'loe 0' and 'lae 4' to load the line number from hol0 and filename from hol0+4.
2016-09-30 17:40:36 +00:00
ine "hol0"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat lim /* Load EM trap ignore mask */
leaving
lde ".ignmask"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sim /* Store EM trap ignore mask */
leaving
ste ".ignmask"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat trp /* Raise EM trap */
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
with REG
Add missing instances of "kills ALL" or "with STACK".
2017-02-13 21:38:26 +00:00
kills ALL
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move %1, r3
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
bl {LABEL, ".trap"}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sig /* Set trap handler */
leaving
ste ".trppc"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat rtt /* Return from trap */
leaving
ret 0
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
/*
* Lexical local base: lxl 0 yields our fp, lxl n yields the
* fp of the nth statically enclosing procedure.
*/
pat lxl $1==0
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
leaving
lor 0
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
pat lxl $1==1
yields {IND_RC_W, fp, SL_OFFSET}
pat lxl $1==2
uses REG={IND_RC_W, fp, SL_OFFSET}
yields {IND_RC_W, %a, SL_OFFSET}
pat lxl $1==3
uses REG={IND_RC_W, fp, SL_OFFSET}, reusing %a, REG
gen move {IND_RC_W, %a, SL_OFFSET}, %b
yields {IND_RC_W, %b, SL_OFFSET}
pat lxl $1>=4 && $1<=0x8000
uses REG={IND_RC_W, fp, SL_OFFSET},
REG={CONST_0000_7FFF, $1-1}
gen
mtspr ctr, %b
1:
lwz %a, {IND_RC_W, %a, SL_OFFSET}
bdnz {LABEL, "1b"}
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
pat dch /* Dynamic chain: LB -> caller's LB */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
yields {IND_RC_W, %1, FP_OFFSET}
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
pat lpb /* LB -> argument base */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
leaving
adp EM_BSIZE
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
pat lxa /* Lexical argument base */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
leaving
lxl $1
lpb
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat gto /* longjmp */
Add missing instances of "kills ALL" or "with STACK".
2017-02-13 21:38:26 +00:00
with STACK
uses REG
gen
move {LABEL, $1}, %a
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move {IND_RC_W, %a, 8}, fp
move {IND_RC_W, %a, 4}, sp
Add missing instances of "kills ALL" or "with STACK".
2017-02-13 21:38:26 +00:00
move {IND_RC_W, %a, 0}, %a
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
mtspr ctr, %a
Add missing instances of "kills ALL" or "with STACK".
2017-02-13 21:38:26 +00:00
bctr.
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
pat lor $1==0 /* Load local base */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses REG
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move fp, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
pat lor $1==1 /* Load stack pointer */
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses REG
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move sp, %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
pat str $1==0 /* Store local base */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move %1, fp
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Implement lxl for PowerPC ncg. This fixes lxl 1 (so it follows the static chain, not the dynamic chain) and provides lxl 2 and greater. The Modula-2 compiler uses lxl for nested procedures, so they can access the variables of the enclosing procedures.
2017-02-14 04:22:31 +00:00
pat str $1==1 /* Store stack pointer */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move %1, sp
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Fix ass to match the EM spec. The spec says, "ASS w: Adjust the stack pointer by w-byte integer". The w argument "can either be given as argument or on top of the stack." Therefore, 'ass 4' would pop the 4-byte integer from the stack, but 'ass' would pop the size w from the stack, then pop the w-byte integer. PowerPC ncg wrongly implemented 'ass' as if it was 'ass 4'. Fix it to accept only 'ass 4'.
2016-12-09 22:32:42 +00:00
pat loc ass $1==4 && $2==4 /* Drop 4 bytes from stack */
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with exact REG
For "pat ass", move fake stack to real stack before adjusting SP. This fixes code that tried to "addi SP, SP, 4" to drop a value that was in a register, not on the real stack. Add a rule to optimize "asp 4" (which becomes "loc 4" "ass") when the value being dropped is already in a GPR.
2016-09-28 04:13:35 +00:00
/* nop */
with STACK
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
addi sp, sp, {CONST, 4}
For "pat ass", move fake stack to real stack before adjusting SP. This fixes code that tried to "addi SP, SP, 4" to drop a value that was in a register, not on the real stack. Add a rule to optimize "asp 4" (which becomes "loc 4" "ass") when the value being dropped is already in a GPR.
2016-09-28 04:13:35 +00:00
Fix ass to match the EM spec. The spec says, "ASS w: Adjust the stack pointer by w-byte integer". The w argument "can either be given as argument or on top of the stack." Therefore, 'ass 4' would pop the 4-byte integer from the stack, but 'ass' would pop the size w from the stack, then pop the w-byte integer. PowerPC ncg wrongly implemented 'ass' as if it was 'ass 4'. Fix it to accept only 'ass 4'.
2016-12-09 22:32:42 +00:00
pat ass $1==4 /* Adjust stack by variable amount */
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST2 STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move {SUM_RC, sp, %1.val}, sp
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
with CONST_HZ STACK
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move {SUM_RC, sp, his(%1.val)}, sp
Tweak some tokens in PowerPC ncg. Remove the GPRINDIRECT token, and use the IND_RC_* tokens as operands to instructions. We no longer need to unpack an IND_RC_* token and repack it as a GPRINDIRECT to use it in an instruction. Allow storing IND_ALL_B and IND_ALL_H in register variables. Create a set ANY_BHW for anything that we can store in a regvar. Push register variables on the stack without using GPRE, by changing stwu to accept LOCAL. Then ncg will replace the string ">>> BUG IN LOCAL" with the register name. (I copied ">>> BUG IN LOCAL" from mach/arm/ncg/table.) Fix the rule for "pat lil inreg($1)>0" to yield a IND_RC_W token, not a register. We might need to kill the token with "kills MEMORY". Rename CONST_ALL to CONST_STACK, because it only includes constants on the stack, and excludes CONST tokens. Instructions still don't allow CONST_STACK operands, so we still need to repack each CONST_STACK as a CONST to use it in an instruction. Rename LABEL_OFFSET_HI to just LABEL_HI, and same for LABEL_HA and LABEL_HO.
2017-02-08 17:12:28 +00:00
with CONST_STACK-CONST2-CONST_HZ STACK
Refactor how powerpc ncg pushes constants. When loc (load constant) pushes a constant, it now checks the value of the constant and pushes any of 7 tokens. These tokens allow stack patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other interesting forms of constants. Use the new constant tokens in the rules for adi, sbi, and, ior, xor. Adjust a few other rules to understand the new tokens. Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC, XOR_RC to GPR no longer touch the scratch register, because the constant is not too big.
2016-10-16 17:58:54 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move {SUM_RC, sp, his(%1.val)}, sp
move {SUM_RC, sp, los(%1.val)}, sp
Trimming mach/powerpc/ncg/table Remove coercion from LABEL to REG. The coercion never happens because I have stopped putting LABEL on the stack. Also remove LABEL from set ANY_BHW. Retain the move from LABEL to REG because pat gto uses it. Remove li32 instruction, unused after the switch to the hi16, ha16, lo16 syntax. Remove COMMENT(...) lines from most moves. In my opinion, they took too much space, both in the table and in the assembly output. The stacking rules and coercions keep their COMMENT(...) lines. In test GPR, don't write to RSCRATCH. Fold several coercions into a single coercion from ANY_BHW uses REG. Use REG instead of GPR in stack patterns. REG and GPR act the same, because every GPR on the stack is a REG, but I want to be clear that I expect a REG, not r0. In code rules, sort SUM_RC before SORT_RR, so I can add SUM_RL later. Remove rules to optimize loc loc cii loc loc cii. If $2==$4, the peephole optimizer can optimize it. If $2!=$4, then the EM program is missing a conversion from size $2 to size $4. Remove rules to store a SEX_B with sti 1 or a SEX_H with sti 2. These rules would never get used, unless the EM program is missing a conversion from size 4 to size 1 or 2.
2017-02-08 17:27:16 +00:00
with REG STACK
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
move {SUM_RR, sp, %1}, sp
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat asp /* Adjust stack by constant amount */
leaving
loc $1
Fix ass to match the EM spec. The spec says, "ASS w: Adjust the stack pointer by w-byte integer". The w argument "can either be given as argument or on top of the stack." Therefore, 'ass 4' would pop the 4-byte integer from the stack, but 'ass' would pop the size w from the stack, then pop the w-byte integer. PowerPC ncg wrongly implemented 'ass' as if it was 'ass 4'. Fix it to accept only 'ass 4'.
2016-12-09 22:32:42 +00:00
ass 4
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Add a test (currently failing) to check that Pascal char sets can store all 256 possible values. Add the PowerPC ncg and mcg backend support to let the test actually run, including modifying a bunch of PowrePC libem functions so that they can be called from both ncg and mcg.
2017-01-15 21:28:14 +00:00
pat lae rck $2==4 /* Range check */
Add a bunch more set operations to the PowerPC backends, and the Pascal test for the same.
2017-01-17 21:31:38 +00:00
with REG
Add missing instances of "kills ALL" or "with STACK".
2017-02-13 21:38:26 +00:00
kills ALL
Add a test (currently failing) to check that Pascal char sets can store all 256 possible values. Add the PowerPC ncg and mcg backend support to let the test actually run, including modifying a bunch of PowrePC libem functions so that they can be called from both ncg and mcg.
2017-01-15 21:28:14 +00:00
gen
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
cmpwi %1, {CONST, rom($1, 1)}
blt {LABEL, ".trap_erange"}
cmpwi %1, {CONST, rom($1, 2)}
bgt {LABEL, ".trap_erange"}
Add a bunch more set operations to the PowerPC backends, and the Pascal test for the same.
2017-01-17 21:31:38 +00:00
yields %1
Add a test (currently failing) to check that Pascal char sets can store all 256 possible values. Add the PowerPC ncg and mcg backend support to let the test actually run, including modifying a bunch of PowrePC libem functions so that they can be called from both ncg and mcg.
2017-01-15 21:28:14 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Floating point support */
/* All very cheap and nasty --- this needs to be properly integrated into
* the code generator. ncg doesn't like having separate FPU registers. */
Check in incomplete Linux PowerPC and M68K work. --HG-- branch : dtrg-experimental-powerpc
2013-05-07 23:48:48 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Single-precision */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zrf $1==INT32 /* Push zero */
leaving
loe ".fs_00000000"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat adf $1==INT32 /* Add single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fadds %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbf $1==INT32 /* Subtract single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fsubs %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat mlf $1==INT32 /* Multiply single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fmuls %a, %2, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dvf $1==INT32 /* Divide single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fdivs %a, %2, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ngf $1==INT32 /* Negate single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fneg %a, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat cmf $1==INT32 /* Compare single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG FSREG
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
uses REG={COND_FS, %2, %1}
gen extlwi %a, %a, {CONST, 2}, {CONST, 0}
yields %a
pat cmf teq $1==4 /* Single second == top */
with FSREG FSREG
uses REG={COND_FS, %2, %1}
gen move {XEQ, %a}, %a
yields %a
pat cmf tne $1==4 /* Single second == top */
with FSREG FSREG
uses REG={COND_FS, %2, %1}
gen move {XNE, %a}, %a
yields %a
pat cmf tgt $1==4 /* Single second > top */
with FSREG FSREG
uses REG={COND_FS, %2, %1}
gen move {XGT, %a}, %a
yields %a
pat cmf tge $1==4 /* Single second >= top */
with FSREG FSREG
uses REG={COND_FS, %2, %1}
gen move {XGE, %a}, %a
yields %a
pat cmf tlt $1==4 /* Single second < top */
with FSREG FSREG
uses REG={COND_FS, %2, %1}
gen move {XLT, %a}, %a
yields %a
pat cmf tle $1==4 /* Single second <= top */
with FSREG FSREG
uses REG={COND_FS, %2, %1}
gen move {XLE, %a}, %a
yields %a
proc cmf4zxx example cmf zeq
with FREG FREG STACK
uses REG
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
fcmpo cr0, %2, %1
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
bxx* {LABEL, $2}
/* Pop 2 singles, branch if... */
pat cmf zeq $1==4 call cmf4zxx("beq")
pat cmf zne $1==4 call cmf4zxx("bne")
pat cmf zgt $1==4 call cmf4zxx("bgt")
pat cmf zge $1==4 call cmf4zxx("bge")
pat cmf zlt $1==4 call cmf4zxx("blt")
pat cmf zle $1==4 call cmf4zxx("ble")
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cff $1==INT32 && $2==INT64 /* Convert single to double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FSREG
yields %1.1
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
/* Convert single to signed int */
pat loc loc cfi $1==4 && $2==4
leaving
loc 4
loc 8
cff
loc 8
loc 4
cfi
/* Convert single to unsigned int */
pat loc loc cfu $1==4 && $2==4
leaving
loc 4
loc 8
cff
loc 8
loc 4
cfu
/* Convert signed int to single */
pat loc loc cif $1==4 && $2==4
leaving
loc 4
loc 8
cif
loc 8
loc 4
cff
/* Convert unsigned int to single */
pat loc loc cuf $1==4 && $2==4
leaving
loc 4
loc 8
cuf
loc 8
loc 4
cff
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Double-precision */
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat zrf $1==INT64 /* Push zero */
leaving
lde ".fd_00000000"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat adf $1==INT64 /* Add double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fadd %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat sbf $1==INT64 /* Subtract double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fsub %a, %2, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat mlf $1==INT64 /* Multiply double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fmul %a, %2, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat dvf $1==INT64 /* Divide double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fdiv %a, %2, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat ngf $1==INT64 /* Negate double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
uses reusing %1, FREG
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
fneg %a, %1
yields %a
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat cmf $1==INT64 /* Compare double */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG FREG
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
uses REG={COND_FD, %2, %1}
gen extlwi %a, %a, {CONST, 2}, {CONST, 0}
yields %a
pat cmf teq $1==8 /* Double second == top */
with FREG FREG
uses REG={COND_FD, %2, %1}
gen move {XEQ, %a}, %a
yields %a
pat cmf tne $1==8 /* Single second == top */
with FREG FREG
uses REG={COND_FD, %2, %1}
gen move {XNE, %a}, %a
yields %a
pat cmf tgt $1==8 /* Double second > top */
with FREG FREG
uses REG={COND_FD, %2, %1}
gen move {XGT, %a}, %a
yields %a
pat cmf tge $1==8 /* Double second >= top */
with FREG FREG
uses REG={COND_FD, %2, %1}
gen move {XGE, %a}, %a
yields %a
pat cmf tlt $1==8 /* Double second < top */
with FREG FREG
uses REG={COND_FD, %2, %1}
gen move {XLT, %a}, %a
yields %a
pat cmf tle $1==8 /* Double second <= top */
with FREG FREG
uses REG={COND_FD, %2, %1}
gen move {XLE, %a}, %a
yields %a
proc cmf8zxx example cmf zeq
with FREG FREG STACK
uses REG
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
fcmpo cr0, %2, %1
Rewrite how PowerPC ncg does conditional branches and tests. The rewritten code rules bring 3 new features: 1. The new rules compare a small constant with a register by reversing the comparison and using `cmpwi` or `cmplwi`. The old rules put the constant in a register. 2. The new rules emit shorter code to yield the test results, without referencing the tables in mach/powerpc/ncg/tge.s. 3. The new rules use the extended `beq` and relatives, not the basic `bc`, in the assembly output. I delete the old tristate tokens and the old moves, because they confused me. Some of the old moves weren't really moves. For example, `move R3, C0` and then `move C0, R0` did not move r3 to r0. I rename C0 to CR0.
2017-01-26 00:08:55 +00:00
bxx* {LABEL, $2}
/* Pop 2 doubles, branch if... */
pat cmf zeq $1==8 call cmf8zxx("beq")
pat cmf zne $1==8 call cmf8zxx("bne")
pat cmf zgt $1==8 call cmf8zxx("bgt")
pat cmf zge $1==8 call cmf8zxx("bge")
pat cmf zlt $1==8 call cmf8zxx("blt")
pat cmf zle $1==8 call cmf8zxx("ble")
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
pat loc loc cff $1==INT64 && $2==INT32 /* Convert double to single */
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
with FREG
uses reusing %1, FSREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Enable the Hall check again, and get powerpc to pass it. Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg gives many errors of "Previous rule impossible on empty stack". David Given reported this problem in 2013: https://sourceforge.net/p/tack/mailman/message/30814694/ Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable the Hall check. This commit enables it again. In ncgg, the Hall check is checking that a rule is possible with an empty fake stack. It would be possible if ncg can coerce the values from the real stack to the fake stack. The powerpc table defined coercions from STACK to {FS, %a} and {FD, %a}, but the Hall check didn't understand the coercions and rejected each rule "with FS" or "with FD". This commit removes the FS and FD tokens and adds a new group of FSREG registers for single-precision floats, while keeping FREG registers for double precision. The registers overlap, with each FSREG containing one FREG, because it is the same register in PowerPC hardware. FS tokens become FSREG registers and FD tokens become FREG registers. The Hall check understands the coercions from STACK to FSREG and FREG. The idea to define separate but overlapping registers comes from the PDP-11 table (mach/pdp/ncg/table). This commit also removes F0 from the FREG group. This is my attempt to keep F0 off the fake stack, because one of the stacking rules uses F0 as a scratch register (FSCRATCH).
2016-09-18 19:08:55 +00:00
frsp %a, %1
yields %a
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
/* Convert double to signed int */
pat loc loc cfi $1==8 && $2==4
with FREG STACK
uses reusing %1, FREG
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
gen
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
fctiwz %a, %1
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
stfdu %a, {IND_RC_D, sp, 0-8}
addi sp, sp, {CONST, 4}
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
/* Convert double to unsigned int */
pat loc loc cfu $1==8 && $2==4
Add missing instances of "kills ALL" or "with STACK".
2017-02-13 21:38:26 +00:00
leaving
cal ".cfu8"
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
/*
* To convert integer to IEEE double, we pack the integer in
* the low bits of the magic double
* 1 << 52 == 0x 4330 0000 0000 0000
*
* For signed integer i, we flip its sign bit, then compute
* ((1 << 52) + i) - ((1 << 52) + (1 << 31))
*/
pat loc loc cif $1==4 && $2==8
with REG
uses reusing %1, REG={XOR_RIS, %1, 0x8000},
REG={CONST_HZ, 0x43300000},
REG={CONST_HZ, 0x80000000},
FREG, FREG
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
stwu %b, {IND_RC_W, sp, 0-8}
stw %a, {IND_RC_W, sp, 4}
lfd %d, {IND_RC_D, sp, 0}
stw %c, {IND_RC_W, sp, 4}
lfd %e, {IND_RC_D, sp, 0}
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
fsub %d, %d, %e
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
addi sp, sp, {CONST, 8}
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
yields %d
Remove trailing whitespace in mach/powerpc/ncg/table
2016-12-09 21:36:42 +00:00
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
/*
* To convert unsigned integer u to IEEE double, we compute
* ((1 << 52) + u) - (1 << 52)
*/
pat loc loc cuf $1==4 && $2==8
with REG
uses REG={CONST_HZ, 0x43300000},
REG={CONST_0000_7FFF, 0},
FREG, FREG
gen
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
stwu %a, {IND_RC_W, sp, 0-8}
stw %1, {IND_RC_W, sp, 4}
lfd %c, {IND_RC_D, sp, 0}
stw %b, {IND_RC_W, sp, 4}
lfd %d, {IND_RC_D, sp, 0}
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
fsub %c, %c, %d
Speed up register allocation by removing some register classes. The table for PowerPC had placed each GPR and FPR into an individual register class (like GPR3, GPR4, FPR1, FPR2), and had used these classes to coerce stack values into specific registers. But ncg does not like having many register classes. In http://tack.sourceforge.net/olddocs/ncg.pdf Hans van Staveren wrote: > Every extra property means the register set is more unorthogonal and > *cg* execution time is influenced by that, because it has to take > into account a larger set of registers that are not equivalent. So > try to keep the number of different register classes to a minimum. Recent changes to the PowerPC table have removed many coercions to specific registers. Many functions in libem switched from taking values in registers to taking them from the stack (see dc05cb2). I now remove all 64 individual register classes of GPR and FPR. In the few cases where I need a stack value in a specific register, I now do a move (as the arm and m68020 tables do). This commit speeds the compilation of some files. For my test file fconv.c, the compilation time goes from over 20 seconds to under 1 second. My fconv.c has 4 conversions from floats to integers, and the table has my experimental rules that do the conversions by allocating 4 or 5 registers.
2017-02-13 22:44:46 +00:00
addi sp, sp, {CONST, 8}
Experiment with conversions between integers and floats. Switch some conversions from libem calls to inline code. The conversions from integers to floats are now too slow, because each conversion allocates 4 or 5 registers, and the register allocator is too slow. I might use these slow conversions to experiment with the register allocator. I add the missing conversions between 4-byte single floats and integers, simply by going through 8-byte double floats. (These replace the calls to nonexistant functions in libem.) I remove the placeholder for fef 4, because it doesn't exist in libem, and our language runtimes only use fef 8.
2017-02-12 04:23:47 +00:00
yields %c
Rewrite .fif8 to avoid powerpc64 fctid This fixes the SIGILL (illegal instruction) in startrek when firing phasers. The 32-bit processors in my PowerPC Mac and in QEMU don't have fctid, a 64-bit instruction. I got the idea from mach/proto/fp/fif8.c to extract the exponent, clear some bits to get an integer, then subtract the integer from the original value to get the fraction.
2016-10-17 04:39:59 +00:00
Change .fef8 and .fif8 to pass values on the stack. Reorder the code in .fef8 and .fif8 so that in the usual case, we fall through to the blr without taking any branches. The usual case, by my guess, is .fef8 with normalized numbers or .fif8 with small integers. I change .fef8 and .fif8 to pass values on the real stack, not in specific registers. This simplifies the ncg table, and might help me experiment with changes to the ncg table. This change might or might not help mcg. Seems that mcg always uses the stack to pass values to libem, but I have not tested .fef8 or .fif8 with mcg.
2017-02-12 21:44:37 +00:00
pat fef $1==8 /* Split fraction, exponent */
leaving
cal ".fef8"
Rewrite .fif8 to avoid powerpc64 fctid This fixes the SIGILL (illegal instruction) in startrek when firing phasers. The 32-bit processors in my PowerPC Mac and in QEMU don't have fctid, a 64-bit instruction. I got the idea from mach/proto/fp/fif8.c to extract the exponent, clear some bits to get an integer, then subtract the integer from the original value to get the fraction.
2016-10-17 04:39:59 +00:00
Change .fef8 and .fif8 to pass values on the stack. Reorder the code in .fef8 and .fif8 so that in the usual case, we fall through to the blr without taking any branches. The usual case, by my guess, is .fef8 with normalized numbers or .fif8 with small integers. I change .fef8 and .fif8 to pass values on the real stack, not in specific registers. This simplifies the ncg table, and might help me experiment with changes to the ncg table. This change might or might not help mcg. Seems that mcg always uses the stack to pass values to libem, but I have not tested .fef8 or .fif8 with mcg.
2017-02-12 21:44:37 +00:00
/* Multiply two doubles, then split fraction, integer */
pat fif $1==8
leaving
cal ".fif8"
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