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Author SHA1 Message Date
David Given 90d0661639 Typo fix. 2016-10-22 00:48:55 +02:00
David Given f851ab83af Better (and more correct) floating point conversions; fif; various new opcodes. 2016-10-22 00:48:26 +02:00
David Given d535be87b1 fef4 and fef8 is now cleaner, albeit slower; add some more register alias 
stuff.
 2016-10-22 00:02:15 +02:00
David Given 4db402f229 Add (pretty crummy) support for register aliases and static pairs of registers. 
We should have enough functionality now for rather buggy 8-bit ints and
doubles. Rework the table and the platform.c to match.
 2016-10-21 23:31:00 +02:00
David Given e4fec71f9c Lots more opcodes; better eviction behaviour; better register moves. Lots more 
PowerPC stuff (some working).
 2016-10-19 23:29:05 +02:00
David Given ffb1eabf45 Floating point promotion is less buggy. 2016-10-19 23:27:53 +02:00
George Koehler 99dee0ad24 Remove f14 to f31 from FREG and FSREG. 
This would have happened later, if f14 to f31 became regvar (like r13
to r31 are now).  I am doing it now because ncg is too slow for rules
"with FREG FREG uses FREG".  We use such rules for adf 8 and other EM
instructions that operate on 2 floats.  Like my last commit cfbc537,
this commit speeds ncg by removing choices for register allocation.
 2016-10-18 21:16:47 -04:00
David Given d5071e7df1 Promote values accessed via NOP. 2016-10-18 23:58:03 +02:00
David Given 5413d47029 '!' tracing is now always emitted; tracing goes to stderr. 2016-10-18 22:32:09 +02:00
David Given 3520704ea8 Add support for floating point constants. 2016-10-18 22:29:42 +02:00
George Koehler cfbc537959 In powerpc ncg, add a speed hack for sti 8. 
ncg is too slow with this many registers.  A stack pattern "with GPR
GPR GPR" or "with REG REG REG" takes too long to pick registers,
causing ncg 8 to take about 2 seconds on each sti 8.  I introduce
REG_PAIR and there are only 4 such pairs.

For programs that use sti 8 (including C programs that copy 8-byte
structs), this speed hack improves the ncg run from several seconds to
almost instantaneous.

Also add a few COMMENT(...) lines in stacking rules.
 2016-10-17 20:31:59 -04:00
David Given 938fb8c2fc Lots more opcodes. 2016-10-18 00:31:26 +02:00
David Given 4a093b9eba Add li and mr pseudoinstructions. 2016-10-18 00:21:32 +02:00
George Koehler c7b68033ef Add costs to powerpc instructions. 
Also show how andi., andis., or., set condition codes.
 2016-10-17 14:57:21 -04:00
George Koehler f33b30ed3c Rewrite .fif8 to avoid powerpc64 fctid 
This fixes the SIGILL (illegal instruction) in startrek when firing
phasers.  The 32-bit processors in my PowerPC Mac and in QEMU don't
have fctid, a 64-bit instruction.

I got the idea from mach/proto/fp/fif8.c to extract the exponent,
clear some bits to get an integer, then subtract the integer from
the original value to get the fraction.
 2016-10-17 00:39:59 -04:00
George Koehler e2ccc8f942 Add "kills MEMORY" to powerpc sti rules. 
Adjust some of the loi rules (and associated moves) so we can identify
the tokens that must be in MEMORY.

With this commit, I can navigate the Enterprise even if I comment out
my work-around from e22c888.
 2016-10-16 18:13:39 -04:00
David Given 5f0164db62 Bolt mcg into the PowerPC backend. It doesn't build yet, but it is generating 
*some* code.
 2016-10-17 00:06:06 +02:00
David Given d539389e81 Merge in the unfinished PowerPC branch. 2016-10-16 22:38:27 +02:00
David Given 1e17921208 Implement saving of dirty registers onto the stack. 2016-10-16 22:37:42 +02:00
George Koehler 19f0eb86a4 Remove IND_LABEL_W and IND_LABEL_D 
Because li32 always loads a label into a GPR, it is sufficient to
coerce LABEL to REG, then use IND_RC_W or IND_RC_D for indirection
through the label.
 2016-10-16 16:33:24 -04:00
George Koehler 5b5f774a64 Simplify moves to and from IND_RC_* 
Now that SUM_RC always has a signed 16-bit constant, it happens that
the various IND_RC_* tokens also have a signed 16-bit constant, so
we no longer need to touch the scratch register.
 2016-10-16 16:02:25 -04:00
George Koehler 7c64dab491 Refactor how powerpc ncg pushes constants. 
When loc (load constant) pushes a constant, it now checks the value of
the constant and pushes any of 7 tokens.  These tokens allow stack
patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned
integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other
interesting forms of constants.

Use the new constant tokens in the rules for adi, sbi, and, ior, xor.
Adjust a few other rules to understand the new tokens.

Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC
each have an unsigned 16-bit constant.  The moves from SUM_RC, OR_RC,
XOR_RC to GPR no longer touch the scratch register, because the
constant is not too big.
 2016-10-16 13:58:54 -04:00
George Koehler baa152217e Remove unused parts of mach/powerpc/ncg/table 
Remove unused tokens GPRINDIRECTLO, HILABEL, LOLABEL, LABELI.  Also
remove an #if 0 ... #endif group of patterns.
 2016-10-15 20:00:48 -04:00
David Given 6a23906ad8 Various bits of cleanup; we should almost be ready to try sending this to the 
assembler soon...
 2016-10-15 23:39:38 +02:00
David Given 286435a2ed Oops, forgot to add the output option spec to the string! 2016-10-15 23:34:54 +02:00
David Given b36897c299 References to the stack frame are now rendered properly. 2016-10-15 23:33:30 +02:00
David Given a8ee82d197 Stop passing proc around, and use a global instead --- much cleaner. 2016-10-15 23:19:44 +02:00
David Given 7aa60a6451 Register spilling to the stack frame works, more or less. 2016-10-15 22:53:56 +02:00
David Given 0eb32e7553 Fix yet another bug to do with IR register outputs. 2016-10-15 19:14:25 +02:00
David Given 9504aec2bd Function termination gets routed through an exit block; we now have prologues 
and epilogues. mcgg now exports some useful data as headers. Start factoring
out some of the architecture-specific bits into an architecture-specific file.
 2016-10-15 18:38:46 +02:00
David Given 5ad3aa8595 Add a pile of new instructions used by Pascal; I'm going to need to think about 
how locals and the local base are handled.
 2016-10-15 13:07:59 +02:00
David Given 358c44de35 Bytes were sometimes failing to be sign extended correctly. 2016-10-15 12:11:40 +02:00
David Given 517120d0fb Allow asm names for registers which are different from the friendly names shown 
in the tracing (because PowerPC register names are just numbers).
 2016-10-15 11:42:47 +02:00
David Given b2ddf12473 Some more opcodes. 2016-10-15 11:22:40 +02:00
George Koehler 29cb008faa In powerpc table, fix macros los() and his(). 
Change the operator in his() from a - minus to a + plus.  When los(n)
becomes negative, then his(n) needs to add 0x10000, not subtract it.

Also change los(n) to do the sign extension, because smalls(los(n))
should be true, not false.

Also change hi(n) and lo(n) to wrap n in parentheses, as (n), because
these are macros and n might still contain operators.
 2016-10-14 23:59:26 -04:00
David Given bb17aea73a You can now mark a register as corrupting a certain register class; calls work, 
or at least look like they work. The bad news is that the register allocator
has a rare talent for putting things in the wrong register.
 2016-10-15 01:15:08 +02:00
David Given 886adb86d7 Log empty hops. 2016-10-14 23:19:25 +02:00
David Given 4f2177e41f Reworked loads and stores; it's now *different*, maybe not better. 2016-10-14 23:19:02 +02:00
David Given a63052427e Factor out the register allocation routines to make them easier to deal with. 2016-10-14 23:17:06 +02:00
David Given bb53a7fb51 Fix stupid issue where hop output registers were being overwritten, leading to 
invalid SSA form.
 2016-10-14 23:12:29 +02:00
David Given 98fe70a7de Output register equality constraints work. 2016-10-14 22:17:02 +02:00
David Given 216ff5cc43 Make loads and stores in the table nicer; fix a place where it looked like it 
was working but only accidentally.
 2016-10-12 23:12:53 +02:00
David Given f06b51c981 Keep track of register types as well as attributes --- the type being how we 
find new registers when evicting values. Input constraints work (they were
being ignored before). Various bug fixing so they actually work.
 2016-10-12 22:58:46 +02:00
David Given 4723a1442f Add code to remove unused phis, converting to pruned SSA form, to avoid 
confusing the register allocator later.
 2016-10-12 21:50:12 +02:00
David Given df239b3f90 Don't allow the same IR to be added to the sequence list more than once 
(sometimes happens because op_dup, but makes no sense).
 2016-10-12 00:45:36 +02:00
David Given 96dffd2007 Clean up the allocator a bit, in preparation for making it lots more 
complicated; no semantic changes.
 2016-10-11 23:17:30 +02:00
David Given 668cccdff1 A few more opcodes. 2016-10-11 00:29:18 +02:00
David Given 2be1c51885 A little fiddling with store instructions. The PowerPC is not friendly to 
iburg.
 2016-10-11 00:23:35 +02:00
David Given e93c58dc8d Refactored the way hops are rendered; add support for emitting code (although 
with no prologue or epilogue yet).
 2016-10-11 00:12:11 +02:00
David Given 92bd1ac5f4 Register allocator now gets all the way through all of my test file without 
crashing (albeit with register moves and swaps stubbed out). Correct code? Who
knows.
 2016-10-10 23:19:46 +02:00
David Given a4d06d1795 D'oh, need multiple passes over the edge splitter in order to properly find all 
cases.
 2016-10-10 23:18:37 +02:00
David Given fac12aae32 Calculate phi congruency groups; use them to solve the 
importing-hreg-from-the-future problem (probably poorly).
 2016-10-09 22:04:20 +02:00
David Given 23c3575f0f The register allocator now makes a spirited attempt to honour register 
attributes when allocating. Unfortunately, backward edges don't work (because
the limited def-use chain stuff doesn't work across basic blocks). Needs more
thought.
 2016-10-09 15:09:34 +02:00
David Given 38de688c5a Floating point promotion was broken since the IR float change. Fix. 2016-10-09 15:08:03 +02:00
David Given 36cddd6afb Add some more opcodes; rearrange the registers to be more PowerPC-friendly. 2016-10-09 14:45:13 +02:00
David Given cfe5312fcc Predicates can now take numeric arguments. The PowerPC predicates have been 
turned into generic ones (as they'll be useful everywhere). Node arguments for
predicates require the '%' prefix for consistency. Hex numbers are permitted.
 2016-10-09 12:32:36 +02:00
David Given d75cc0a663 Basic register allocation works! 2016-10-08 23:32:54 +02:00
David Given 637aeed70a Only allocate an output vreg if the instruction actually wants one. 2016-10-08 12:15:21 +02:00
David Given 2198db69b1 Instruction predicates work now. 2016-10-08 11:35:33 +02:00
David Given 9ebf731335 Minor cleanup. 2016-10-08 11:07:28 +02:00
David Given 9db902314b Fix bug where pushes were being placed in the wrong blocks. 2016-10-08 10:21:24 +02:00
George Koehler 65c2a8a0ae Remove stackadjust and stackoffset() from ncg. 
This feature has never been used since its introduction, more than 3
years ago, in David Given's commit c93cb69 of May 8, 2013.  The commit
was for "PowerPC and M68K work".  I am not undoing the entire commit.
I am only removing the stackadjust and stackoffset() feature.

This commit removes the feature from my branch kernigh-linuxppc.  This
removal includes the mach/proto/ncg parts.  The default branch already
removed most of the feature, but kept the mach/proto/ncg parts.  That
removal happened in commit 81778b6 of May 13, 2013 (which was a merge;
git diff af0dede 81778b6).  The branch dtrg-experimental-powerpc
merged the default branch but without the removal.  That merge was
commit 4703db0f of Sep 15, 2016 (git diff 8c94b13 4703db0).  My branch
kernigh-linuxppc is off branch dtrg-experimental-powerpc, so I can no
longer get the removal by merging default.

David Given described the stackadjust feature in
  https://sourceforge.net/p/tack/mailman/message/30814691/

The instruction stackadjust would add a value to the offset, and the
function stackoffset() would return this offset.  One would use this
to track sp - fp, then omit the frame pointer by not keeping fp in a
register.
 2016-10-07 20:52:13 -04:00
David Given 4e49830e09 Overhaul of everything phi related; critical edge splitting now happens before 
anything SSA happens; liveness calculations now look like they might be
working.
 2016-10-08 00:21:23 +02:00
George Koehler 409ba7fb1b Remove most of GPRE from mach/powerpc/ncg/table 
We only need GPRE in a few places where we write {GPRE, regvar(...)}
because ncgg can't parse plain regvar(...).  In all other places, a
plain GPR works.

Also remove gpr_gpr_gpr and a few other unused and fake instructions
from the list of instructions.
 2016-10-06 22:59:27 -04:00
George Koehler 7cccd88b71 Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH. 
Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I
can search for RSCRATCH without finding FSCRATCH.  I also want to
avoid confusion with the SCRATCH keyword of the old code generator (cg
which came before ncg).

Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH
or any other GPR or FPR that isn't an allocatable REG or FREG.  Then
ncgg rejects any rule that tries to stack a GPR or FPR, so change such
rules to stack a REG or FREG.
 2016-10-06 20:47:42 -04:00
David Given ee93389c5f Refactor the cfg and dominance stuff to make it a lot nicer. 2016-10-06 21:34:21 +02:00
David Given d20b63dc94 The register allocator is really a pass, so arrange the code like one. 2016-10-05 23:55:38 +02:00
David Given 87e004e4a9 Warning fix. 2016-10-05 23:55:04 +02:00
David Given 21034c0d65 No, dammit, for register allocation I need to walk the blocks in *dominance* 
order. Since the dominance tree has changed when I fiddled with the graph, I
need to recompute it, so factor it out of the SSA pass. Code is uglier than I'd
like but at least the RET statement goes last in the generated code now.
 2016-10-05 23:52:54 +02:00
David Given d95c75dfd7 Allowing an input filename on the command line makes debuggers happy. (Then we 
don't need to redirect stdin.)
 2016-10-05 23:24:29 +02:00
David Given 88fb231d6e Better constraint syntax; mcgg now passes register usage information up to mcg; 
mcg can track individual hop inputs and outputs (needed for live range
analysis!); the register allocator now puts the basic blocks into the right
order in preparation for live range analysis.
 2016-10-05 22:56:25 +02:00
David Given 7a6fc7a72b Made sure that all files end in vim magic. 2016-10-05 21:07:29 +02:00
David Given 92502901a7 Better management of register data. Add struct hreg. 2016-10-05 21:00:28 +02:00
David Given ac62c34e19 Add a pass to do critical edge splitting. 2016-10-04 23:42:00 +02:00
David Given 8fedf5a0a8 Added support for the op_bXX conditional branch instructions. 2016-10-04 23:28:16 +02:00
David Given 249855ed23 Fix the horror of the startup code; now uses getopt and stuff and the debug 
flags can be set as an option.
 2016-10-04 22:36:01 +02:00
David Given ac063a6f54 Remove unused variable (reduce memory usage by 1/10). 2016-10-04 22:35:08 +02:00
David Given c6f576f758 Bodge in enough phi support to let the instruction generator complete on basic 
programs.
 2016-10-04 21:58:31 +02:00
David Given e13ff5be31 Don't allocate new vregs for REG and NOP --- a bit hacky, but suppresses stray 
movs very effectively.
 2016-10-04 21:29:03 +02:00
David Given bd28bddb92 Massive rewrite of how emitters and the instruction selector works, after I 
realised that the existing approach wasn't working. Now, hopefully, tracks the
instruction trees generated during selection properly.
 2016-10-04 00:16:06 +02:00
David Given 68f98cbad7 Instruction selection now happens on a shadow tree, rather than on the IR tree 
itself. Currently it's semantically the same but the implementation is cleaner.
 2016-10-03 20:52:36 +02:00
David Given 288ee56203 Get quite a long way towards basic output-register equality constraints (needed 
to make special nodes like NOP work properly). Realise that the way I'm dealing
with the instruction selector is all wrong; I need to physically copy chunks of
tree to give to burg (so I can terminate them correctly).
 2016-10-02 23:25:54 +02:00
David Given 3aa30e50d1 Come up with a syntax for register constraints. 2016-10-02 21:51:25 +02:00
David Given c079e97492 Perform SSA conversion of locals. Much, *much* better code now, at least 
inasmuch as it looks better before register allocation. Basic blocks now know
their own successors and predecessors (after a certain point in the IR
processing).
 2016-10-02 17:50:34 +02:00
David Given 79d4ab1d96 Add zrl opcode. Keep track of local sizes as well as offsets. 2016-10-02 16:08:46 +02:00
David Given bf73fcdb64 Add inl and del opcodes. 2016-10-02 14:44:21 +02:00
David Given b298c27c63 Refactor mcg.h as it's getting a bit big; keep track of register variables. 2016-10-02 00:30:33 +02:00
David Given 06059233da Make betterer. 2016-10-01 23:41:45 +02:00
David Given 65e75be42d Fix edge case where leftover pushes would occasionally cause infinite loops in 
the analysis.
 2016-10-01 23:41:35 +02:00
David Given 73d7e89c32 Show expression trees correctly. 2016-10-01 23:41:03 +02:00
David Given 3474e20274 Deal with malformed mes instructions emitted by ego. 2016-10-01 23:13:39 +02:00
David Given a3cfe6047f More rigorous dealing of IR groups; no need for is_generated and is_root any 
more (but now passes are required to set IR roots properly when changing
instructions).
 2016-10-01 22:58:29 +02:00
David Given 21898f784a We're going to need some type inference after all, I think. Let's do a little 
for now and see how it goes.
 2016-10-01 19:10:22 +02:00
David Given 91e277e046 Predicates work; we now have prefers and requires clauses. Predicates must be 
functions. Not convinced that semantic types are actually working --- there are
still problems with earlier statements leaving things in the wrong registers.
 2016-10-01 13:56:52 +02:00
David Given 4a3a9a98dc It doesn't really make a lot of sense to have BURG nonterminal names different 
to register classes, so combine them. Refactor the map code.
 2016-10-01 12:17:14 +02:00
George Koehler ce5faba919 Remove .linenumber and .filename; use hol0 and hol0+4. 
We need this because some .e files in lang/ are using 'loe 0' and 'lae
4' to load the line number from hol0 and filename from hol0+4.
 2016-09-30 13:40:36 -04:00
David Given 3a973a19f3 Move fatal(), warning() and aprintf() into the new data module (because they're 
really useful).
 2016-09-30 19:10:30 +02:00
George Koehler e22c8881e7 Add a rule for sdl ldl $1==$2 to work around a bug. 
In our powerpc table, sdl fails to kill the old value of the local.
This is a bug, because a later ldl can load the old value instead of
the newly stored value.  By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl
0", the newly added rule works around the bug, but only when the ldl
is immediately after the sdl.

This rule improves code that uses double-precision floating point.
The output of printf("%f", 6.0) in C changes from all zero digits to
"6000000" but still doesn't print the decimal point.  The result of
atof("-123.456") becomes correct.  In startrek, I can now move the
Enterprise, but I still can't fire phasers without crashing the game.

We already have a rule for stl lol $1==$2.  We had two copies of the
rule, so I am deleting the second copy.
 2016-09-30 11:50:50 -04:00
David Given 0d246c0d73 Much better handling of fragments (no run-time code needed to distinguish them 
from registers) and better handling of individual hops within a paragraph ---
no more ghastly hacks to try and distinguish the input from the output.
 2016-09-29 22:06:04 +02:00
George Koehler 6ae415d48b Rewrite fef 8 in powerpc assembly. 
In EM, fef splits a float into exponent and fraction.  The old C code,
given an infinite float, got stuck in an infinite loop.  The new
assembly code doesn't loop; it extracts the IEEE exponent.
 2016-09-29 15:52:54 -04:00
David Given a0131fdb47 You know what, the type inference stuff is a complete red herring. What this 
actually needs is a more intelligent register allocator. So, remove the type
inference.
 2016-09-29 19:58:02 +02:00
George Koehler a71eee3914 For "pat ass", move fake stack to real stack before adjusting SP. 
This fixes code that tried to "addi SP, SP, 4" to drop a value that
was in a register, not on the real stack.

Add a rule to optimize "asp 4" (which becomes "loc 4" "ass") when
the value being dropped is already in a GPR.
 2016-09-28 00:13:35 -04:00
David Given 4572f1b774 Actually, I don't need vregs: hops work just as well. Particularly if I 
restructure things so that I don't need to walk the blasted ir / burg tree
every time I look at an instruction.
 2016-09-27 23:38:47 +02:00
George Koehler 1e3dde915a Remove the "invalid" stacking rule. 
When ncg fell back on this rule, it did emit the string "invalid" in
the assembly code and caused a syntax error in the assembler.

Adjust the stacking rules so we can stack LOCAL, CONST, and LABEL
without falling back on the "invalid" rule, and so we can stack them
when we have no free register except the scratch register.
 2016-09-27 16:46:11 -04:00
David Given e77c5164cf Fleshed out hops and vregs. The result is almost looking like code now --- 
uncanny.
 2016-09-27 00:19:45 +02:00
David Given f552c9c7c6 Move map into the data module. 2016-09-26 23:03:04 +02:00
David Given c4b8e00ae2 Revamp the array module not to use nasty macros any more. Slightly more verbose 
to use, but definitely cleaner.
 2016-09-26 22:48:58 +02:00
David Given 3671892c34 Move the array library into the data module. 2016-09-26 22:24:49 +02:00
David Given cc176e5183 Keep more data around about ir instructions. Implement a half-baked type 
inference routine to propagate information about floats up the tree, so we know
whether to put floats into special registers as early as possible.
 2016-09-26 22:12:46 +02:00
David Given 416b13fd76 Start factoring out the hardware op code. 2016-09-25 23:29:59 +02:00
David Given 39aa672422 Sort of keep track of registers and register classes. Start walking the 
generated instruction tree --- holy cow, they look like instructions!
 2016-09-25 22:17:14 +02:00
David Given bde5792b1a Collapse several rule arrays into one; actually generate the array properly. 2016-09-25 17:14:54 +02:00
David Given 67eb21d428 Rename struct insn to struct em (throughout). 2016-09-25 12:29:03 +02:00
David Given 9f78e0b36b Rethink the way patterns are mapped to rules; generate emitters (probably 
badly).
 2016-09-25 11:49:51 +02:00
David Given 7c028bdd45 We now record the code fragments to be emitted by each rule. 2016-09-25 00:21:46 +02:00
David Given 717b77dd0a Instruction selection is so important the file needs a longer name. 2016-09-24 22:50:53 +02:00
David Given 629e0ddfc6 Some instruction selection is now happening. 2016-09-24 22:46:08 +02:00
David Given c8fcbe282a More grammar changes. 2016-09-24 19:03:55 +02:00
David Given 2acc4ed29d IR codes are now owned by mcgg; ir terminals are inserted into the table during 
compilation (so you can refer to them).
 2016-09-24 18:31:35 +02:00
David Given 1516657907 Crudely bolt on mcgg to mcg itself. 2016-09-24 17:20:40 +02:00
David Given 6643d39b2c Fix some late-night typo bugs. 2016-09-24 01:09:32 +02:00
David Given bb9aa030a5 Procedure compilation now happens after the entire EM file has been read in (so 
that we can look inside data blocks which might be defined in the future...
sigh, csa and csb). csa and csb no longer generate invalid IR.
 2016-09-24 01:04:00 +02:00
David Given ed67d427c9 Replaced the block splicer with a trivial block eliminator (which rewrites 
jumps to blocks which contain only a jump). Don't bother storing the bb graph
in the ir nodes; we can find it on demand by walking the tree instead ---
slower, but much easier to understand and more robust. Added a terrible map
library.
 2016-09-23 23:59:15 +02:00
David Given f8bbf9e87d Each pass now lives in its own source file; much cleaner. 2016-09-23 21:07:16 +02:00
David Given 9077baa850 Add a bodged in algorithm for converting basic block communication from stacked 
variables to SSA. Also add dead block removal and block splicing. IR code is
much better now.
 2016-09-22 23:19:29 +02:00
David Given 6a74cb2e11 Tracing cleanup. Simplified the IR code. Some more opcodes. 2016-09-22 00:15:48 +02:00
David Given 4546dd5f22 Massive grammar overhaul and refactor. Hacked in support for predicates, where 
instructions can be turned on and off based on their parameters. New lexer
using a lexer. Now quite a lot of the way towards being a real instruction
selector.
 2016-09-21 00:43:10 +02:00
David Given 36d7d1ee4e Create hacky fake basic blocks for data fragments, used to track which 
instruction labels descriptor blocks refer to; this allows csa and csb to know
where they're going.
 2016-09-20 00:19:39 +02:00
David Given dcba03646b Treebuilder now gets to the bottom of my test file, merrily generating 
(probably horribly broken) IR.
 2016-09-19 23:30:41 +02:00
David Given 6ce2495aeb Store the EM code up front and build the basic block graph *before* 
generating the IR code. Lots more IR code.
 2016-09-19 23:06:59 +02:00
David Given 176cd7365c Archival checking of the half-written IR treebuilder. 2016-09-18 23:24:54 +02:00
George Koehler 5b69777647 Rename our pseudo-opcode 'la' to 'li32'. 
GNU as has "la %r4,8(%r3)" as an alias for "addi %r4,%r3,8", meaning
to load the address of the thing at 8(%r3).  Our 'la', now 'li32',
makes an addis/ori pair to load an immediate 32-bit value.  For
example, "li32 r4,23456789" loads a big number.
 2016-09-18 17:03:23 -04:00
George Koehler 9db305b338 Enable the Hall check again, and get powerpc to pass it. 
Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg
gives many errors of "Previous rule impossible on empty stack".  David
Given reported this problem in 2013:
  https://sourceforge.net/p/tack/mailman/message/30814694/

Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable
the Hall check.  This commit enables it again.  In ncgg, the Hall
check is checking that a rule is possible with an empty fake stack.
It would be possible if ncg can coerce the values from the real stack
to the fake stack.  The powerpc table defined coercions from STACK to
{FS, %a} and {FD, %a}, but the Hall check didn't understand the
coercions and rejected each rule "with FS" or "with FD".

This commit removes the FS and FD tokens and adds a new group of FSREG
registers for single-precision floats, while keeping FREG registers
for double precision.  The registers overlap, with each FSREG
containing one FREG, because it is the same register in PowerPC
hardware.  FS tokens become FSREG registers and FD tokens become FREG
registers.  The Hall check understands the coercions from STACK to
FSREG and FREG.  The idea to define separate but overlapping registers
comes from the PDP-11 table (mach/pdp/ncg/table).

This commit also removes F0 from the FREG group.  This is my attempt
to keep F0 off the fake stack, because one of the stacking rules uses
F0 as a scratch register (FSCRATCH).
 2016-09-18 15:08:55 -04:00
George Koehler 03b067e1d5 Add the missing .lar4 and .sar4 for powerpc. 
Inspired by the sparc code (mach/sparc/libem/lar.s).  My powerpc code
might still have bugs, but it's enough for examples/hilo.mod to work.

May need to 'make clean' or touch a build.lua file, so ackbuilder can
notice the new lar4.s and sar4.s files and build them.
 2016-09-17 23:55:55 -04:00
David Given 24380e2a93 Abstract out the EM reader; skeleton of the tree builder. 2016-09-18 00:02:16 +02:00
David Given 2eee391aef Basic skeleton of em parser. 2016-09-17 22:21:47 +02:00
David Given 80cb6ba927 Eliminate the RELOH2 relocation, as it never worked --- the address would be 
calculated incorrectly because of overflow errors.

Replace it with an extended RELOPPC relocation which understands addis/ori
pairs; add an la pseudoop to the assembler which generates these and the
appropriate relocation. Make good.

--HG--
branch : dtrg-experimental-powerpc-branch
 2016-09-17 12:43:15 +02:00
David Given 45a950571d Mostly add support for the experimental and largely broken linuxppc platform. 
(Doesn't quite build.)

--HG--
branch : dtrg-experimental-powerpc-branch
 2016-09-15 23:12:03 +02:00
David Given f67c98e239 Distributions are a pain --- let's not bother any more. Instead, we just tag 
the repository and download a complete snapshot, old and ancient stuff and all.
 2016-09-02 23:00:38 +02:00
David Given 612e38f1c6 Remove the old make-based build system, plus some big chunks of horribly 
obsolete protomake build system.
 2016-09-02 22:17:51 +02:00
David Given 856eb120b3 Add files which got missed in the initial build pass. 2016-08-20 14:04:17 +02:00
David Given 204f932ed2 Raspberry Pi backend now builds. 2016-08-20 12:40:13 +02:00
David Given 4d24666432 Move util/data into modules/src/em_data, for consistency with the other 
modules.
 2016-08-14 14:09:38 +02:00
David Given 38fa6941d5 linux68k builds now. 2016-08-14 11:34:18 +02:00
David Given f253b6a169 linux386 builds. Also, forgot to turn back on the language runtimes. 2016-08-14 10:37:55 +02:00
David Given 262c5fedcf Biggish refactor to break cycles; my build rules were full of them. cpm builds, 
which requires top and topgen.
 2016-08-14 01:39:40 +02:00
David Given 0d77cb8279 We can build our first C file. 2016-08-07 21:56:53 +02:00
David Given b50dc4214a Add check for undefined variables. Find undefined variables. Fix undefined 
variables.
 2016-08-05 00:01:55 +02:00
David Given 5e84be70fd Massive ackbuilder refactor --- cleaner and more expressive. Lists 
are automatically flattened (leading to better build files), and the
list and filename functions are vastly more orthogonal.
 2016-08-04 23:51:19 +02:00
David Given b2bb4ce3b2 Builds libend (the simplest library). Becoming obvious I need to rework the way 
ackbuilder deals with lists.
 2016-07-30 00:39:22 +02:00
David Given a8a9d1bbfa yacc, ncgg; platform ncg builds now. 2016-07-26 23:35:30 +02:00
David Given bff5c4019c Baby steps towards building a platform --- make the assembler work. 
Add ackbuilder support for C preprocessor files and yacc.
 2016-07-24 00:50:02 +02:00
David Given 88bd7ce126 Remove defunct pmfiles. 
--HG--
branch : default-branch
 2016-06-03 13:56:50 +02:00
David Given ef8e6e25e0 Fix a whole pile of issues related to the failed attempt to increase 
the number of types of relocation possible in the object file. (Now,
hopefully, working.)

Also change the object serialiser/deserialiser to never try to read or
write raw structures; it's way safer this way and we don't need the
performance boost any more.

--HG--
branch : default-branch
 2016-03-18 21:46:55 +01:00
David Given 88e13ecce3 Don't use the ACK preprocessor on host files --- use the host preprocessor 
instead.

--HG--
branch : default-branch
 2016-03-14 20:58:19 +01:00
David Given e85991ec86 Fix stray 'call file'. 
--HG--
branch : default-branch
 2016-03-13 21:40:05 +01:00
David Given ff0c78cc78 Merge from default. 
--HG--
branch : dtrg-videocore-branch-branch
 2016-03-13 21:13:09 +01:00
David Given 62cc636f10 Merge. 
--HG--
branch : dtrg-videocore
 2015-03-23 00:15:42 +01:00
David Given 9f23fbbe6a Allow machines to use cg if they wish. 
--HG--
rename : mach/proto/ncg/build.mk => mach/proto/cg/build.mk
rename : util/ncgg/build.mk => util/cgg/build.mk
 2015-03-23 00:08:51 +01:00
David Given c5018d7088 64-bit-ify (adhoc varargs are evil). 2015-03-23 00:07:59 +01:00
David Given 3d5e72e20b Newer versions of GNU Make have a new function which collides with a 
variable we're using; change the name of the variable.
 2015-03-22 12:09:46 +01:00
David Given e36d739fa4 Add (largely untested) float/int conversion. 
--HG--
branch : dtrg-videocore
 2013-07-01 13:05:36 +01:00
David Given 8b6951dac0 Fix incorrect offset encoding in lea (sp) instructions. 
--HG--
branch : dtrg-videocore
 2013-06-29 00:35:07 +01:00
David Given edb174da8d Fix incorrect encoding of 'push lr' and 'pop pc'. 
--HG--
branch : dtrg-videocore
 2013-06-29 00:32:39 +01:00
David Given 29af6f1adb ISA change: clz has been renamed to log2. 
--HG--
branch : dtrg-videocore
 2013-06-27 11:25:50 +01:00
David Given 2b3f95de0b Fix jump range checking in the addcmpb family of instructions. 
--HG--
branch : dtrg-videocore
 2013-06-26 23:32:54 +01:00
David Given d94c1c8150 Updated distr files. 
--HG--
branch : dtrg-videocore
rename : mach/i80/.distr => mach/vc4/.distr
rename : plat/cpm/.distr => plat/rpi/.distr
 2013-06-21 23:38:21 +01:00
David Given fd2360be0f Ship assembler man pages. 
--HG--
branch : dtrg-videocore
rename : man/8080_as.6 => man/i80_as.6
rename : man/m68k2_as.6 => man/m68020_as.6
 2013-06-21 23:20:50 +01:00
David Given bbd4b46850 Fix stack corruption when adjusting SP. Be a bit more rigorous about clearing the pseudostack on branch/labels. 
--HG--
branch : dtrg-videocore
 2013-06-07 21:25:38 +01:00
David Given 3e0123ca03 Fix treatment of out-of-range values in switch csa. 
--HG--
branch : dtrg-videocore
 2013-06-05 23:57:23 +01:00
David Given 86c6fa2f1e Implement NOT... 
--HG--
branch : dtrg-videocore
 2013-05-30 23:50:19 +01:00
David Given d3e3e72860 Update from trunk. 
--HG--
branch : dtrg-videocore
 2013-05-29 15:03:48 +01:00
David Given e0c121d6e6 Use relocation enumerations rather than hard-coded values for relocation types 
(these were causing problems due to the enumeration values having changed).
 2013-05-29 14:11:04 +01:00
David Given 1f36370d87 Implement nop (the C compiler sometimes generates this!). 
--HG--
branch : dtrg-videocore
 2013-05-26 22:54:53 +01:00
David Given ef25c53c9c Fix bug in ine/dee. 
--HG--
branch : dtrg-videocore
 2013-05-26 18:59:19 +01:00
David Given 366cd10194 Remainders are calculated correctly. printf now works. 
--HG--
branch : dtrg-videocore
 2013-05-26 13:13:58 +01:00
David Given 510888e6d5 .csb now works. 
--HG--
branch : dtrg-videocore
rename : mach/vc4/libem/csa.s => mach/vc4/libem/csb.s
 2013-05-26 13:06:25 +01:00
David Given 6284512b37 Fix erroneous section check (symbols may not have a defined section in pass 1). 
--HG--
branch : dtrg-videocore
 2013-05-26 00:35:15 +01:00
David Given 308d41e083 Added triple-quad load and store (used by the signal stuff). 
--HG--
branch : dtrg-videocore
 2013-05-26 00:22:08 +01:00
David Given 8c21a2ef9b Stop fighting the terrible code and remove the regvar support --- it didn't help much and was a pain. 
--HG--
branch : dtrg-videocore
 2013-05-25 23:58:35 +01:00
David Given 3b07fee160 Major bugfix where instructions weren't being shrunk correctly. (Turns out there's built-in support for doing this, which I hadn't found.) 
--HG--
branch : dtrg-videocore
 2013-05-25 23:26:10 +01:00
David Given b6680a48cc Disable register variables. The code is a bit worse, but having two stackable registers makes things much easier to understand. 
--HG--
branch : dtrg-videocore
 2013-05-25 13:31:58 +01:00
David Given d7efb0a32c Implement .csa. 
--HG--
branch : dtrg-videocore
rename : mach/vc4/libem/dummy.s => mach/vc4/libem/csa.s
 2013-05-25 13:31:27 +01:00
David Given 2ee79ab0b2 Encode comparing branch correctly. 
--HG--
branch : dtrg-videocore
 2013-05-25 13:31:01 +01:00
David Given 472f778342 Don't write out constant data as big-endian! Some other cleanups. 
--HG--
branch : dtrg-videocore
 2013-05-25 00:33:38 +01:00
David Given 98a51732ab Various codegen tweaks. 
--HG--
branch : dtrg-videocore
 2013-05-24 17:04:29 +01:00
David Given 2c7ee27206 Double-quads can be loaded and stored (more) correctly. 
--HG--
branch : dtrg-videocore
 2013-05-22 23:55:23 +01:00
David Given 6cbe6e1c4e Better treatment of sign extension. 
--HG--
branch : dtrg-videocore
 2013-05-22 23:12:48 +01:00
David Given 7537c85e0a Generate adds instructions when a shift-and-add is seen (useful for array indexing). 
--HG--
branch : dtrg-videocore
 2013-05-22 21:37:48 +01:00
David Given cdce394b6c Generate ld rd, (rs) instructions properly. 
--HG--
branch : dtrg-videocore
 2013-05-22 11:02:46 +01:00
David Given 9e556d8b7b Optimise direct access to globals, and incrementing and decrementing locals. 
--HG--
branch : dtrg-videocore
 2013-05-22 10:55:13 +01:00
David Given 08c4334224 Typo fixes. 
--HG--
branch : dtrg-videocore
 2013-05-22 00:44:04 +01:00
David Given f904465e9c Fix signedness problem that was showing up on ARM. 
--HG--
branch : dtrg-videocore
 2013-05-22 00:16:16 +01:00
David Given 5e9102955c Reworked VC4 relocations and some of the instruction encoding to be actually correct. Now generating what could be real code! 
--HG--
branch : dtrg-videocore
 2013-05-21 23:17:30 +01:00
David Given 1312fe298b Now compiles (incorrectly) the entire libc, libpc, libm2 and libbasic! 
--HG--
branch : dtrg-videocore
 2013-05-21 20:05:26 +01:00
David Given 877e06ed89 Lots more opcodes including float support. Define float and double to be the 
same thing (as the VC4 seems not to have double-precision float support).

--HG--
branch : dtrg-videocore
 2013-05-21 18:16:30 +01:00
David Given 6cdea73e84 Add a lot more opcodes. 
--HG--
branch : dtrg-videocore
 2013-05-20 23:27:45 +01:00
David Given d6565f4d5b Fix typo. 
--HG--
branch : dtrg-videocore
 2013-05-20 23:27:31 +01:00
David Given 970f2bae62 Major revamp to simplify and use 2op instructions. Better code. Now looks like it may work one day. 
--HG--
branch : dtrg-videocore
 2013-05-20 22:35:12 +01:00
David Given 5082b2a5d7 Add lea instruction. Fix dependency issues. 
--HG--
branch : dtrg-videocore
 2013-05-20 19:56:33 +01:00
David Given 11890026db Push/pop are the right way round. Don't corrup short-form ALU instructions. Correct encoding of push/pop register ranges. 
--HG--
branch : dtrg-videocore
 2013-05-19 23:34:42 +01:00
David Given 76ba0bf6b3 First steps towards a code generator. 
--HG--
branch : dtrg-videocore
 2013-05-19 23:33:42 +01:00
David Given 80f85001fa Correctly emit constants in some ALU instructions. 
--HG--
branch : dtrg-videocore
 2013-05-19 23:19:10 +01:00
David Given a46ee91859 Fix warning. 
--HG--
branch : dtrg-videocore
 2013-05-19 23:18:36 +01:00
David Given 4f15423d63 Add compare-and-branch instructions. 
--HG--
branch : dtrg-videocore
 2013-05-19 18:40:19 +01:00
David Given 80afe75c9b Added memory operations that work on fixed up addresses. 
--HG--
branch : dtrg-videocore
 2013-05-19 13:03:53 +01:00
David Given febe8ca937 Add register offset and postincrement memory operations. 
--HG--
branch : dtrg-videocore
 2013-05-19 12:39:35 +01:00
David Given fc2833d456 Add most vanilla memory load/store instructions. 
--HG--
branch : dtrg-videocore
 2013-05-19 00:56:56 +01:00
David Given 26877d3c4f Add a whole bunch of VC4 opcodes. 
--HG--
branch : dtrg-videocore
 2013-05-17 23:30:49 +01:00
David Given 5b4aa07dee Merge fixes from trunk. 
--HG--
branch : dtrg-videocore
 2013-05-17 15:28:04 +01:00
David Given e7c2029c9c Dependency fixes. 2013-05-17 00:04:37 +01:00
David Given 32ebc502c8 Skeleton of VideoCore IV support for the Raspberry Pi. 
--HG--
branch : dtrg-videocore
rename : mach/powerpc/as/.distr => mach/vc4/as/.distr
rename : mach/powerpc/as/mach0.c => mach/vc4/as/mach0.c
rename : mach/powerpc/as/mach1.c => mach/vc4/as/mach1.c
rename : mach/powerpc/as/mach2.c => mach/vc4/as/mach2.c
rename : mach/powerpc/as/mach3.c => mach/vc4/as/mach3.c
rename : mach/powerpc/as/mach4.c => mach/vc4/as/mach4.c
rename : mach/powerpc/as/mach5.c => mach/vc4/as/mach5.c
rename : mach/i86/build.mk => mach/vc4/build.mk
rename : mach/powerpc/libem/powerpc.h => mach/vc4/libem/videocore.h
rename : mach/i86/libend/.distr => mach/vc4/libend/.distr
rename : mach/i86/libend/edata.s => mach/vc4/libend/edata.s
rename : mach/i86/libend/em_end.s => mach/vc4/libend/em_end.s
rename : mach/i86/libend/end.s => mach/vc4/libend/end.s
rename : mach/i86/libend/etext.s => mach/vc4/libend/etext.s
rename : mach/powerpc/ncg/.distr => mach/vc4/ncg/.distr
rename : mach/powerpc/ncg/mach.c => mach/vc4/ncg/mach.c
rename : mach/powerpc/ncg/mach.h => mach/vc4/ncg/mach.h
rename : mach/powerpc/ncg/table => mach/vc4/ncg/table
rename : plat/pc86/descr => plat/rpi/descr
 2013-05-17 00:03:38 +01:00
David Given e5f6d5acfa Fix buffer overrun looking up type information for op_lab pseudoops (as 
they're not EM opcodes, we shouldn't look them up in em_flags!).
 2013-05-16 22:02:59 +01:00
David Given 24ef1627ec A few last build tweaks. 
--HG--
branch : dtrg-buildsystem
 2013-05-16 14:20:58 +01:00
David Given 11377070fd Update distribution files. 
--HG--
branch : dtrg-buildsystem
 2013-05-15 23:46:15 +01:00
David Given 8fbce949f5 Now describe the make-based build system in the README. 
--HG--
branch : dtrg-buildsystem
 2013-05-15 23:12:05 +01:00
David Given a68b117e96 Add missing dependency. 
--HG--
branch : dtrg-buildsystem
 2013-05-14 14:55:29 +01:00
David Given 07453d184a Top, topgen, aelflod. Moved the libraries back into the platform-specific 
directories --- wrangling descr files was too hard. C programs can be built
for cpm, pc86, linux386, linux68k!

--HG--
branch : dtrg-buildsystem
rename : util/ack/build.mk => util/led/build.mk
rename : util/LLgen/build.mk => util/topgen/build.mk
 2013-05-13 23:26:15 +01:00
David Given 442306d557 Split off some of the platform-independent stuff (such as as and ncg). 
--HG--
branch : dtrg-buildsystem
rename : plat/pc86/build.mk => mach/i386/build.mk
rename : plat/pc86/build.mk => mach/i80/build.mk
rename : plat/pc86/build.mk => mach/i86/build.mk
rename : plat/pc86/build.mk => mach/m68020/build.mk
rename : plat/pc86/build.mk => mach/powerpc/build.mk
 2013-05-13 22:12:46 +01:00
David Given b0c238eb5d Made a start on building the runtimes for each platform and language; the 
Linuxes all build.

--HG--
branch : dtrg-buildsystem
rename : modules/src/em_mes/build.mk => modules/src/read_em/build.mk
rename : plat/pc86/build.mk => plat/linux386/build.mk
rename : plat/pc86/build.mk => plat/linux68k/build.mk
rename : plat/pc86/build.mk => plat/linuxppc/build.mk
rename : util/ack/build.mk => util/misc/build.mk
 2013-05-12 23:51:55 +01:00
David Given c1aca7dae5 First milestone of replacing the build system. 
--HG--
branch : dtrg-buildsystem
rename : lang/cem/cpp.ansi/Parameters => lang/cem/cpp.ansi/parameters.h
 2013-05-12 20:45:55 +01:00
David Given bcfb3d802f Add pmfile for m68020 libend. 
--HG--
branch : dtrg-experimental-powerpc
 2013-05-09 00:58:35 +01:00
David Given 8e2d027c49 Add pmfile for m68020 libem. 
--HG--
branch : dtrg-experimental-powerpc
 2013-05-09 00:57:47 +01:00
David Given c93cb69959 Check in incomplete Linux PowerPC and M68K work. 
--HG--
branch : dtrg-experimental-powerpc
 2013-05-08 00:48:48 +01:00
George Koehler 0131ca4d46 Delete 689 undead files. 
These files "magically reappeared" after the conversion from CVS to
Mercurial.  The old CVS repository deleted these files but did not
record *when* it deleted these files.  The conversion resurrected these
files because they have no history of deletion.  These files were
probably deleted before year 1995.  The CVS repository begins to record
deletions around 1995.

These files may still appear in older revisions of this Mercurial
repository, when they should already be deleted.  There is no way to fix
this, because the CVS repository provides no dates of deletion.

See http://sourceforge.net/mailarchive/message.php?msg_id=29823032
 2012-09-20 22:26:32 -04:00
dtrg 481bcd8a8b Added a very-nearly-noop peephole optimiser for Z80. 2008-03-20 23:20:08 +00:00
dtrg fc44fe2185 Properly handles files ending in a partial line. 2008-03-20 22:50:50 +00:00
dtrg 4dd1ff6d80 Archival checkin (semi-working code). 2007-11-02 18:56:58 +00:00
cvs2hg 58e5e12ead fixup commit for tag 'release-6-0-pre-3' 2007-04-29 23:09:25 +00:00
dtrg 54ce3f451b Configured distr system for the 6.0pre3 release. 2007-04-29 23:09:24 +00:00
dtrg 663f4f2fb5 Cleaned up a bit and made work with the new platform architecture. 2007-04-29 23:03:24 +00:00
dtrg df088c184b Added optimised rules for int<<8 and uint>>8 (which can be done with simple register shuffling rather than calling .sli). 2007-04-29 23:00:31 +00:00
dtrg be8baf3da6 Added cpm platform. 2007-04-27 22:42:41 +00:00
dtrg 440d6faadd Fixed a bug where loc lol stf was getting the constant pushed onto the stack *after* stf had popped it off. 2007-04-27 22:15:31 +00:00
dtrg 24ea8aee3d Updated for the 6.0pre2 release. 2007-04-24 20:45:58 +00:00
dtrg 04860c08a8 Updated to work with the linux386 platform. 2007-04-21 22:57:51 +00:00
dtrg daee8da3c4 yacc source files are now run through the ANSI C preprocessor, not the K&R one. 2007-04-21 22:55:59 +00:00
dtrg 4428647786 Everything is built in ANSI C now. 2007-04-21 22:55:04 +00:00
dtrg b611731ec3 Updated .distr files for the new release. 2007-02-25 12:51:55 +00:00
dtrg f6a41864cf Moved to /h. 2007-02-25 12:45:24 +00:00
dtrg 5c5f711cbb Done a major overhaul of the way target include files are installed and 
how platform libraries are built. The ARCH pm variable has now been
renamed PLATFORM (which is more accurate) and a different ARCH
variable added, which represents the CPU family rather than the
hardware platform.
 2007-02-20 00:46:10 +00:00
dtrg 809cd2ef0b Added a definition of endrom. 2007-02-20 00:42:23 +00:00
dtrg 5165f0b11f Added some comments and a CVS header. 2007-02-20 00:41:26 +00:00
dtrg c21ba9ed0f Updated to work with the new version of pm. 2006-11-11 22:59:52 +00:00
dtrg dbe10d2c19 Updated to the version 0.1 of Prime Mover (which involves some syntax changes). 2006-10-15 00:28:12 +00:00
dtrg 9bcefaafa8 Broke dependency on tool_cpp in order to speed up the build. 2006-07-30 23:41:16 +00:00
dtrg 014be56fb0 Replaced calls to the custom strindex() and strrindex() functions with the 
exactly equivalent and standard strchr() and strrchr() functions instead.
 2006-07-23 20:01:02 +00:00
dtrg 304c0e21a0 Added support for the top target peephole optimiser. 2006-07-22 12:31:19 +00:00
dtrg fdcdaadcb8 Rationalised use of #includes to be more standards-compliant. 2006-07-22 12:28:20 +00:00
dtrg 1a037b9685 Added support for the ego global optimisation suite. 2006-07-22 00:52:01 +00:00